Semiconductor device having MOS transistor
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsYouji Kawasaki, Taketo Takahashi, Takashi Murakami
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AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsYouji Kawasaki, Taketo Takahashi, Takashi Murakami
Estimating the term…
A semiconductor device which can effectively prevent impurity diffusion in heat treatment for electrically activating the impurity, and a manufacturing method thereof are disclosed. In the semiconductor device, a diffusion preventing layer having a depth equal to or greater than a junction depth of source/drain regions is formed along the entire junction region of the source/drain regions. The diffusion preventing layer is formed near the surface at the side of a gate insulation layer of the gate electrode including impurity.
A semiconductor device, comprising:
A semiconductor device, comprising:
Dependencies are inferred from the claim text.
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From the US filing history. Foreign family members aren’t listed.
1. Field of the Invention
The present invention relates generally to semiconductor devices and a method of manufacturing the same and, more particularly, to a semiconductor device having an MOS (Metal-Oxide-Semiconductor) transistor and a manufacturing method thereof.
2. Description of the Background Art
FIG. 1 is a cross-sectional view showing a semiconductor device including a P channel MOS transistor according to a first embodiment of the present invention.
FIGS. 2 through 9 are cross-sectional views showing the first to eighth steps of manufacturing the semiconductor device of the first embodiment shown in FIG. 1.
FIG. 10 is a graph showing the relation between the diffusion depth immediately after implantation and nitrogen concentration in the nitrogen implantation step shown in FIG. 7.
Embodiments of the present invention will be described in the following with reference to the figures.
FIG. 1 is a cross-sectional view showing a semiconductor device including a P channel MOS transistor according to a first embodiment of the present invention.
Referring to FIG. 1, in the semiconductor device according to the first embodiment, an insulation oxide film 2 is formed at a predetermined region on the main surface of an N type silicon substrate 1. Source/drain regions 6a and 6b are formed with a predetermined distance therebetween to sandwich a channel region 10 on the main surface of silicon substrate 1 surrounded by insulation oxide film 2. A gate electrode 4 formed of a polycrystalline silicon film including impurity is formed on a channel region 10 with a gate oxide film 3 having the thickness of 500-2000 .ANG. posed therebetween. Sidewall oxide films 5 are formed at both sidewall portions of gate electrode 4.
Characterised by the semiconductor materials: into Group IV semiconductors
Of FETs having insulated gates [IGFET]: having source and drain regions or source and drain extensions self-aligned to sides of the gate
Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions: emitter…
Source or drain regions of field-effect devices: of igfets
Term ended 28 Mar 2014 (estimated)
USPTO file history isn’t available for this patent, so only indexed dates are shown.