US 5,514,880 A · Field effect thin-film transistor for an SRAM with reduced standby current

Abstract

In a miniaturized complete CMOS SRAM of a TFT load type, a field effect thin-film transistor (TFT) can achieve stable reading and writing operation of a memory cell and can reduce power consumption thereof. The field effect thin-film transistor formed on an insulator includes an active layer and a gate electrode. The gate electrode is formed on a channel region of the active layer with a gate insulating film therebetween. The active layer is formed of a channel region and source/drain regions. The channel region is formed of a monocrystal silicon layer and does not includes a grain boundary. The source/drain regions is formed of a polysilicon layer. The channel region has a density of crystal defects of less than 10.sup.9 pieces/cm.sup.2. The thin film transistor shows an ON current of 0.25 .mu.A/.mu.m per channel width of 1 .mu.m and an OFF current of 15 fA/.mu.m. The thin-film transistor can be applied to a p-channel MOS transistor serving as a load transistor in a memory cell of a CMOS type SRAM.

Claims15

Dependent claims

A field effect thin-film transistor formed on an insulator, comprising:

a semiconductor thin film including a portion which forms a channel region having a predetermined channel width, the channel region being formed on the insulator;
source and drain regions formed in portions of said semiconductor thin film which are isolated from each other in a direction crossing said channel width by said channel region;
a gate insulating film formed on said channel region;
and
a gate electrode formed on said gate insulating film;
wherein
said channel region of said semiconductor thin film is formed of a crystal structure controlled such that a current flowing between said source and drain regions attains a value of -0.25 .mu.A or more per channel width of 1 .mu.m if voltage of -3 V is applied across said source and drain regions and a voltage of -3 V is applied across said gate electrode and said source region, and attains a value of -15 fA or less per channel width of 1 .mu.m if a voltage of -3 V is applied across said source and drain regions and a voltage of 0 V is applied across said gate electrode and said source region.

4 more elements

A semiconductor device, comprising:

a first conductivity-type semiconductor substrate having a main surface;
a second conductivity-type field effect transistor formed on the main surface of said semiconductor substrate;
and
a first conductivity-type field effect transistor electrically connected to said second conductivity-type field effect transistor,
wherein said first conductivity-type field effect transistor includes:
a semiconductor thin film including a portion which forms a channel region having a predetermined channel width, the channel region being formed on the insulator;
source and drain regions of the first conductivity-type formed in portions of said semiconductor thin film which are isolated from each other in a direction crossing said channel width by said channel region;
a gate insulating film formed on said channel region;
and
a gate electrode formed on said gate insulating film;
wherein
said channel region of said semiconductor thin film is formed of a crystal structure controlled such that a current flowing between said source and drain region attains a value of -0.25 .mu.A or more per channel width of 1 .mu.m if a voltage of -3 V is applied across said source and drain regions and a voltage of -3 V is applied across said gate electrode and said source region, and attains a value of -15 fA or less per channel width of 1 .mu.m if a voltage of -3 V is applied across said source and drain regions and a voltage of 0 V is applied across said gate electrode and said source region.

9 more elements

A static-type semiconductor memory device provided with a memory cell having a complementary field effect transistor, comprising:

a first conductivity-type semiconductor substrate having a main surface;
and
a plurality of memory cells formed on the main surface of said semiconductor substrate,
wherein each of said memory cells includes:
first and second driver transistors formed, respectively, of second conductivity-type field effect transistors on the main surface of said semiconductor substrate and having the gate electrodes and the drain electrodes cross-coupled, and
first and second load transistors formed, respectively, of first conductivity-type field effect transistors connected, respectively, to the drain electrodes of said first and second driver transistors,
wherein each of said first and second load transistors includes:
a semiconductor thin film including a portion which forms a channel region having a predetermined channel width, the channel region being formed on the insulator;
source and drain regions of the fist conductivity-type formed in portions of said semiconductor thin film which are isolated from each other in a direction crossing said channel width by said channel region;
a gate insulating film formed on said channel region;
and
a gate electrode formed on said gate insulating film;
wherein said channel region of said semiconductor thin film is formed of a crystal structure controlled such that a current flowing between said source and rain regions attains a value of -0.25 .mu.A or more per channel width of 1 .mu.m if a voltage of -3 V is applied across said source and drain regions and a voltage of -3 V is applied across said gate electrode and said source region, and attains a value of -15 fA or less per channel width of 1 .mu.m if a voltage of -3 V is applied across said source and drain regions and a voltage of 0 V is applied across said gate electrode and said source region.

10 more elements

Dependencies are inferred from the claim text.

Field effect thin-film transistor for an SRAM with reduced standby current

Life of this patent

Field effect thin-film transistor for an SRAM with reduced standby current

Life of this patent

Abstract

Claims15