Parallel manufacturing of semiconductor devices and the resulting structure

A method of manufacturing an integrated circuit comprising the steps of:

• (i) forming a plurality of first parts of integrated circuits in a semiconductor substrate;
• (ii) separately forming an interconnect structure;
• (iii) forming a plurality of dice from said semiconductor substrate, each of said dice comprising one of said first parts, said one of said first parts having a top surface and having contacts on said top surface;
• (iv) forming a plurality of interconnect substructures from said interconnect structure for use with said dice, each interconnect substructure being a second integrated circuit part, each interconnect substructure comprising one or more interconnect layers, each interconnect substructure having a bottom surface and a top surface opposite the bottom surface, one of said interconnect layers being on the top surface of each interconnect substructure, each interconnect substructure further comprising contacts on the bottom surface at locations corresponding to the locations of the contacts on said one of said first parts;
• and
• (V) joining one of said plurality of interconnect substructures to a corresponding one of said plurality of dice to form the integrated circuit, said joining step including joining the contacts on the bottom surface of said one interconnect substructure to the contacts on the top surface of said one of said first parts so that the top surface of the interconnect substructure becomes the top surface of the integrated circuit and said one interconnect layer is on the top surface of the integrated circuit and is connected by electrically conductive material to said one of said first parts.

A method of manufacturing an integrated circuit comprising the steps of:

• (i) forming a plurality of first parts of integrated circuits in a semiconductor substrate;
• (ii) forming a plurality of dice from said semiconductor substrate, each of said dice including one of said first parts, said one of said first parts having a top surface and having contacts on said top surface;
• (iii) separately forming a second part of the integrated circuit comprising an interconnect structure comprising one or more interconnect layers, said interconnect structure having a bottom surface and a top surface opposite the bottom surface, one of said interconnect layers being on the top surface of the interconnect structure, said interconnect structure further comprising contacts on the bottom surface at locations corresponding to the locations of the contacts on said one of said parts;
• and
• (iv) joining said interconnect structure to one of said plurality of dice to form the integrated circuit, said joining step including joining the contacts on the bottom surface of the interconnect structure to the contacts on the top surface of said one of said first parts so that the top surface of the interconnect structure becomes the top surface of the integrated circuit and said one interconnect layer is on the top surface of the integrated circuit and is connected by electrically conductive material to said one of said first parts.

A method of manufacturing an integrated circuit comprising the steps of:

• (i) forming a first part of the integrated circuit in a semiconductor substrate, said first part comprising a plurality of dice, each of said dice having a top surface and having contacts on said top surface;
• (ii) inspecting said semiconductor substrate for good dice;
• (iii) separately forming a second part of the integrated circuit comprising an interconnect structure, comprising one or more interconnect layers, for use with the semiconductor substrate, said interconnect structure having a bottom surface and a top surface opposite the bottom surface, one of said interconnect layers being on the top surface of the interconnect structure;
• (iv) fabricating said interconnect structure to mate only with said good dice, the contacts on the bottom surface of the interconnect structure corresponding to the contacts on said good dice;
• and
• (v) joining said interconnect structure to said semiconductor substrate to form the integrated circuit, said joining step including joining the contacts on the interconnect structure to the contacts on said good dice so that the top surface of the interconnect structure becomes the top surface of the integrated circuit and so that said one interconnect layer is on the top surface of the integrated circuit and is electrically connected to said good dice.

A method of manufacturing an integrated circuit comprising the steps of:

• (i) forming a plurality of semiconductor dice, each die containing part of an integrated circuit, each die having a top surface and having contacts on said top surface;
• (ii) separately forming an interconnect structure containing a plurality of interconnect substructures for use with said plurality of semiconductor dice, each interconnect substructure comprising one or more interconnect layers, each interconnect substructure having a bottom surface and a top surface opposite the bottom surface, one of said interconnect layers being on the top surface of each interconnect substructure, each interconnect substructure further comprising contacts on the bottom surface at locations corresponding to the locations of the contacts on the top surface of one of said plurality of dice;
• (iii) inspecting said interconnect structure for good interconnect substructures;
• (iv) removing from said interconnect structure said good interconnect substructures;
• and
• (v) joining one of said good interconnect substructures to one of said semiconductor dice to form the integrated circuit, said joining step including joining the contacts on the bottom surface of said one good interconnect substructure to the contacts on said one semiconductor die so that the top surface of the interconnect substructure becomes the top surface of the integrated circuit and said one interconnect layer is on the top surface of the integrated circuit and is connected by electrically conductive material to said one semiconductor die.