Method of making an optimized code ion implantation procedure for read only memory devices
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYeh-Jye Wann, Jue-Jye Chen
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Abstract
A process designed to fabricate depletion mode MOSFET devices, for ROM applications, has been developed. A key feature of this fabrication sequence is the ion implantation step used to create the programmable cell. The code implant step is performed through a polysilicon gate structure, into the underlying channel region. The ability to reproducibly place the desired dopant at the desired channel location, is dependent on the implant conditions as well as the reproducibility of the thicknesses of the layers the implant has to penetrate. This process has been designed to remove some of the variables and thus result in optimized device characteristics.
Claims18
A method of fabricating a Read Only Memory, (ROM), cell on a semiconductor substrate comprising the steps of:
- forming a field oxide pattern on specific regions of said substrate while leaving bare silicon on remaining regions of said substrate;
- growing a gate oxide on said bare silicon;
- depositing a polysilicon layer on said gate oxide, and on said field oxide pattern;
- ion implanting a first conductivity imparting dopant into said polysilicon layer;
- patterning to form polysilicon gate structure, from said polysilicon layer, on said gate oxide and on said field oxide pattern;
- removal of said gate oxide from regions not covered by said polysilicon gate structure, to expose regions of said bare silicon;
- depositing a first insulator layer on said polysilicon gate structure, on said field oxide pattern, not covered by said polysilicon gate structure, and on said bare silicon;
- anisotropically etching of said first insulator layer to form a spacer insulator on sidewall of said polysilicon gate structure;
- growing a screen oxide on said polysilicon gate structure, and on said bare silicon;
- ion implanting a second conductivity imparting dopant into said polysilicon gate structure, and into said bare silicon, through said screen oxide;
- photolithography to expose specific region of the silicon chip, consisting of said polysilicon gate structures, and regions of said bare silicon;
- removal of said screen oxide from said polysilicon gate structure, and from said bare silicon, in said specific region of the silicon chip, exposed by photolithography;
- and
- ion implanting a third conductivity imparting dopant through said polysilicon gate structure, and through said gate oxide.
A method of fabricating a Read Only Memory, (ROM), cell, on a semiconductor substrate comprising the steps of:
- forming a field oxide pattern on specific regions of said substrate, while leaving bare silicon on remaining regions of said substrate;
- growing a gate oxide on said bare silicon;
- depositing a polysilicon layer on said gate oxide, and on said field oxide pattern;
- ion implanting a first conductivity imparting dopant into said polysilicon layer;
- patterning to form polysilicon gate structure, from said polysilicon layer, on said gate oxide and on said field oxide pattern;
- removal of said gate oxide from regions not covered by said polysilicon gate structure, to expose regions of said bare silicon;
- depositing a first insulator layer on said polysilicon gate structure, on said field oxide pattern, not covered by said polysilicon gate structure, and on said bare silicon;
- anisotropically etching of said first insulator layer to form a spacer insulator on sidewall of said polysilicon gate structure;
- growing a screen oxide on said polysilicon gate structure, and on said bare silicon;
- ion implanting a second conductivity imparting dopant, through said screen oxide, into said polysilicon gate structure, and into said bare silicon to form source and drain areas;
- photolithography to expose specific region of the silicon chip, to be used for the programmable cell, consisting of specific said polysilicon gate structures, and specific said source and drain regions;
- removal of said screen oxide from said polysilicon gate structure, and from said source and drain areas, in said specific regions of silicon chip to be used for programmable cell;
- and
- ion implanting a third conductivity imparting dopant, rough said polysilicon gate structure, through said gate oxide, to form depletion mode, programmable cell.
Dependencies are inferred from the claim text.