Method of fabricating high breakdown voltage FETs
AssigneeMotorola, Inc.
InventorsMajid M. Hashemi, Saied N. Tehrani
Life of this patent
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Abstract
A method of fabricating high breakdown voltage MESFETs forming a conduction channel in a GaAs substrate adjacent the surface, forming high temperature stable source and drain ohmic contacts and a Schottky gate contact on the surface of the substrate in overlying relationship to the channel and in spaced relationship, and depositing a layer of low temperature GaAs passivation material over the substrate surface and the source, drain and gate contacts. Openings are then etched in the passivation material for contacting the source, drain and gate contacts.
Claims9
A method of fabricating high breakdown voltage FETs comprising the steps of:
- providing a substrate of semi-insulating GaAs having a surface;
- forming a gate contact on the surface of the substrate between predetermined source and drain regions including depositing a refractory metal to form a Schottky contact with the surface of the substrate;
- doping the substrate to form a conduction channel in the substrate adjacent the surface and at least in the source and drain regions;
- forming source and drain contacts on the surface of the substrate in overlying relationship to the conduction channel and in the predetermined source and drain regions, respectively, including depositing a refractory metal to form ohmi contacts with the surface of the substrate;
- depositing a layer of low temperature GaAs passivation material over the substrate surface and the source, drain and gate contacts;
- and
- removing some of the passivation material to expose portions of the source, drain and gate contacts to allow external connections thereto.
A method of fabricating high breakdown voltage FETs comprising the steps of:
- providing a substrate having a surface;
- forming a conduction channel in the substrate adjacent the surface;
- forming a gate contact on the surface of the substrate in overlying relationship to the channel and between the source and drain contacts;
- implanting a dopant in the conduction channel to define source and drain regions in the conduction channel on opposite sides of the gate contact;
- annealing the source and drain regions at a temperature in the range of 750.degree.to 900.degree. Centigrade to activate the implant;
- forming source and drain contacts on the surface of the source and drain regions in overlying relationship to the channel subsequent to the annealing of the source and drain regions;
- and
- forming a layer of low-temperature-grown GaAs passivation material over the substrate surface and the source, drain and gate contacts.
A method of fabricating high breakdown voltage FETs comprising the steps of:
- providing a substrate of semi-insulating GaAs including a plurality of epitaxially grown layers with at least a conduction channel layer and a contact layer positioned thereon so as to form an exposed surface of the contact layer;
- forming a groove through the contact layer so as to expose a portion of a surface of the conduction channel layer;
- forming source and drain contacts on the exposed surface of the contact layer and on opposite sides of the groove;
- forming a gate contact in the groove on the exposed surface of the conduction channel layer and between the source and drain contacts;
- and
- depositing a layer of low temperature GaAs passivation material over the substrate surface, the groove and the source, drain and gate contacts.
Dependencies are inferred from the claim text.