System for compensating data rate between a storage device and a data compression processor using a buffer memory mapped twice into contiguous address space of a host processing unit

A system for compensating for data rate differences between a storage device and a data compression processor comprising:

• a host control processing unit including a bus having an address space and a local memory;
• an addressable compressed data buffer including a first port and a second port, the first port being coupled to the data compression processor wherein the data buffer is twice mapped into the address space of the host control processing unit to provide a contiguous buffer memory;
• a direct memory access address register connected to the data buffer, which stores data addresses of a location within the data buffer;
• a direct memory access limit register connected to the data buffer which limits a direct memory access transfer of data between the compression processor and the compressed data buffer;
• a data interface linking the second port of the data buffer, the host control processing unit, the local memory and the storage device;
• whereby a data transfer between the storage device and the addressable compressed data buffer is accomplished by passing the data through the host control processing unit only once, and without storing the data in the local memory of the host control processing unit.

A system for transferring data between a data compression processor and a storage device, comprising:

• a controller unit including a bus having an address space;
• an addressable compressed data buffer which is twice mapped into the address space of the controller unit to provide a contiguous buffer memory;
• a data interface linking the addressable compressed data buffer, the controller unit, the storage device and the compression processor;
• and
• whereby a data transfer between the storage device and the data compression processor is accomplished by passing the data through the controller unit only once.