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US 5,513,364 AGranted
Data transfer device and multiprocessor system
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorJunji Nishikawa
Life of this patent
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Abstract
In a data transfer control device for controlling a data transfer bus connected to plural buffer units, an address generation circuit for specifying a buffer unit address is provided with an address register for holding upper and lower limit values of the buffer unit address, an address counter which sequentially increments the buffer unit address, starting from the lower limit value, and a comparator for judging whether an output of the address counter reaches to the upper limit value. The data transfer control device composes a crossbar-type data transfer network together with the buffer units, and plural processor elements or plural I/O devices are connected to the network.
Claims29
A data transfer device having a plurality of buffer units connected to a common data transfer bus and a data transfer control device for outputting continually onto the data transfer bus a buffer unit address for sequentially selecting buffer units in an arbitrary number out of the plural buffer units and for governing control of data transfer, via the data transfer bus, between buffer units selected by the buffer unit address, said data transfer control device comprising:
- a memory means for storing a first address and a second address, said first address indicative of either an upper limit address or a lower limit address of the buffer unit address, and said second address indicative of either of the upper limit address or the lower limit address of the buffer unit address not indicated by said first address;
- an update means for holding the first address provided from said memory means and for outputting the thus held first address as the buffer unit address, while sequentially updating the thus held first address;
- a comparison means for outputting a conformity signal upon conformity of the buffer unit address outputted from said update means with the second address provided from said memory means;
- and
- a control means for sequentially providing an address update requirement signal to said update means so that said update means executes address update and for providing an address setting signal to said update means, upon receipt of an output of the conformity signal from said comparison means, so as to set the first address held by said memory means to said update means.
2 more elements
A multiprocessor system comprising:
- buffer units of N.sup.2 in number which are respectively arranged at two-dimensional lattice points expressed by a coordinate (x, y), x, y=0-N-1 (N.gtoreq.2);
- first data transfer buses of N in number each of which is commonly connected to the buffer units of N in number which are arranged in X direction out of said N.sup.2 buffer units;
- second data transfer buses of N in number each of which is commonly connected to the buffer units of N in number which are arranged in Y direction out of said N.sup.2 buffer units;
- data transfer control devices of 2N in number which are connected to each of said first data transfer buses and said second data transfer buses;
- and
- processor elements of N in number each having a first data transfer port connected to one of the N data transfer control devices connected to the extreme end of the first data transfer buses out of the 2N data transfer control devices and a second data transfer port connected to one of the N data transfer control devices connected to the second data transfer buses out of the 2N data transfer control devices,
- wherein each of the 2N data transfer control devices includes:
- memory means for holding first and second addresses for specifying a range of buffer unit address for sequentially selecting buffer units of an arbitrary number out of the N buffer units commonly connected to the data transfer control devices out of the N.sup.2 buffer units;
- update means for holding the first address provided from said memory means and for outputting the thus held first address as the buffer unit address, while sequentially updating the thus held first address;
- comparison means for outputting a conformity signal upon conformity of the buffer unit address outputted from said update means with the second address provided from said memory means;
- and
- control means for providing sequentially an address update requirement signal to said update means so that said update means executes address update and for providing an address setting signal to said update means, upon receipt of an output of the conformity signal from said comparison means, so as to set the first address held by said memory means to said update means.
9 more elements
A multiprocessor system comprising:
- buffer units of N.sup.3 in number which are respectively arranged at lattice points of three-dimension expressed by a coordinate (x, y, z), x, y, z=0-N-1 (N.gtoreq.2);
- first data transfer buses of N.sup.2 in number each of which is commonly connected to the N buffer units arranged in X direction out of the N.sup.3 buffer units;
- second data transfer buses of N.sup.2 in number each of which is commonly connected to the N buffer units arranged in Y direction out of the N.sup.3 buffer units;
- data transfer control devices of 2N.sup.2 in number which are connected to each of said first data transfer busses and said second data transfer buses;
- and
- processor elements of N.sup.2 in number each having a first data transfer port connected to one of the N.sup.2 data transfer control devices connected to said first data transfer buses out of the 2N.sup.2 data transfer control devices and a second data transfer port connected to one of the N.sup.2 data transfer control devices connected to said second data transfer buses out of the 2N.sup.2 data transfer control devices,
- wherein each of said 2N.sup.2 data transfer control devices includes:
- memory means for holding first and second addresses for specifying a range of a buffer unit address for sequentially selecting buffer units of an arbitrary number out of the N buffer units commonly connected to said data transfer control devices out of the N.sup.3 buffer units;
- update means for holding the first address provided from said memory means and for outputting the thus held first address as the buffer unit address, while sequentially updating the thus held first address;
- comparison means for outputting a conformity signal upon conformity of the buffer unit address outputted from said update means with the second address provided from said memory means;
- and
- control means for sequentially providing an address update requirement signal to said update means so that said update means executes address update and for providing an address setting signal to said update means, upon receipt of the conformity signal from said comparison means, so as to set the first address held by said memory means to said update means.
9 more elements
Dependencies are inferred from the claim text.