Scalable register file organization for a computer architecture having multiple functional units or a large register file

A microprocessor comprising:

• a plurality of functional units;
• and
• a scalable register file having a plurality of read ports, each read port being coupled to a respective functional unit, the register file including at least first and second pipeline register stages;
• the first and second pipeline register stages including:
• a multiported micro-register file having a plurality of read ports, each port of the micro-register file corresponding to a respective functional unit;
• a plurality of pipelined instruction registers for holding instructions, each instruction register corresponding to a respective functional unit,
• an instruction decoder coupled to the plurality of instruction registers for selecting registers required by each functional unit as specified by the instruction held in the corresponding instruction register;
• a plurality of pipeline registers, each pipeline register coupled to a corresponding output port of the micro-register file to receive the contents of the selected registers,
• each instruction register of the first pipeline register stage being coupled to a corresponding instruction register of the second pipeline register stage, and each pipeline register of the first pipeline register stage being coupled to a corresponding pipeline register of the second pipeline register stage;
• and
• enable logic to present the contents of the pipeline registers of the first pipeline register stage to the corresponding pipeline register of the second pipeline register stage during a second pipeline cycle, if there were contents stored in the pipeline registers of the first pipeline register stage during a first pipeline cycle.

A method of minimizing access time of a register file for a computer architecture having a large number of registers or multiple functional units, the method comprising:

• partitioning the register file into a first micro-register file having a first subset of the register file and a second micro-register file having a second subset of the register file, each register of the register file having contents stored therein;
• selecting registers in the first micro-register file during a first pipeline cycle;
• storing the contents of the registers which were selected during the first pipeline cycle;
• selecting registers in the second micro-register file during a second pipeline cycle subsequent to the first pipeline cycle;
• and
• storing the contents of the registers which were selected during the second pipeline cycle and the stored contents of the registers selected during the first pipeline cycle.

A pipelined register file for a computer architecture having multiple functional units, comprising:

• a first stage including at least
• a first micro-register file including a first plurality of registers and a plurality of output ports, each of the output ports being associated with a respective one of the functional units, and
• a plurality of first pipeline registers, each of the first pipeline registers being coupled to a respective one of the output ports of the first micro-register file;
• a second stage including at least
• a second micro-register file including a second plurality of registers and a plurality of output ports, each of the output ports being associated with a respective one of the functional units, and
• a plurality of second pipeline registers, each of the first pipeline registers being coupled to a respective one of the output ports of the second micro-register file;
• and
• means for selecting data for each of the functional units from one of the first micro-register file and the second micro-register file.