Cache control system which permanently inhibits local but not global parameter data writes to main memory
AssigneeKabushiki Kaisha Toshiba
InventorAkihisa Fujimoto
Life of this patent
Estimating the term…
Abstract
A data cache memory is dynamically allocated as a global area which can be accessed in tasks other than a current task, and a local area which can be accessed in only a specific task. In the global area, data processing is controlled by the write through or copy back technique, in the same manner as in a conventional system. With respect to an access to the local area, an access is allowed to only the data cache memory, but is inhibited in relation to a main memory. For this reason, the tag section of the data cache memory includes a flag indicating a local or global area, and a task number storage field indicating a task in which a secured local area is accessed.
Claims27
A data cache memory control system having a main memory, a data cache memory in which part of said main memory is copied, and a central processing unit (CPU) for accessing said main memory and said data cache memory, comprising:
- data cache memory allocating means for allocating at least a global area for storing global parameters and a local area for storing localparameters in said data cache memory, the global area being accessed in any one of a plurality of modules constituting a program, and the local area being accessed in a specific module, said CPU writing global parameters in the global area and said main memory, and reading the global parameters from said main memory when the global parameters are not found in the global area;
- local area access detecting means for detecting whether an access to the local area is performed;
- and
- memory access means for permanently inhibiting contents of the local area from being written into said main memory when the access to the local area is performed, and means for writing the local parameters only in the local area.
A data processing apparatus comprising:
- a central processing unit (CPU);
- a main memory;
- data cache memory means in which part of said main memory is copied and which outputs a "HIT" signal when data, access to which is requested by said CPU, is found;
- memory bus control means for supplying no address signal to said main memory when a "HIT" signal is output from said data cache memory means;
- local area securing instruction execution detecting means for detecting that said CPU executes an instruction of securing a local area in a stack;
- means for securing a local area in said data cache memory, in accordance with a detection of said local area securing instruction execution detecting means;
- and
- means for outputting a "HIT" signal to said memory bus control means if data, which are requested by the CPU, are found in the local area, so that said memory bus control means supplies no address signal to said main memory to permanently inhibit contents of said local area from being written into said main memory.
In a data cache memory control system having a main memory, a data cache memory in which part of the main memory is copied, and a central processing unit (CPU) for accessing the main memory and the data cache memory, a method for securing a local variable area being accessed in a specific module in the data cache memory, comprising the steps of:
- a) monitoring an instruction executed by the CPU;
- b) comparing the data of the instruction with an operation code of a certain fetched operation instruction;
- c) outputting an instruction detection signal upon coincidence in step b);
- d) securing the local variable area in the cache memory in accordance with the instruction detection signal when the CPU executes the operation instruction;
- e) comparing an access address of the instruction with a tag address of the data cache memory to determine if requested data is in the cache memory;
- f) determining whether the tag address is in the local variable area when a coincidence is obtained in step e);
- g) storing the data in the data cache memory, when step f) indicates the existence of the tag address in the local variable area;
- and
- h) permanently inhibiting the CPU from writing contents of the local variable area into the main memory.
A data cache memory control system, comprising:
- a central processing unit (CPU);
- a main memory;
- a data cache memory having at least a local variable area for storing local parameters in a stack, the local variable area being accessed by the CPU in a procedure of an application program;
- detecting means for detecting whether or not a memory read/write access with a stack operation instruction is performed;
- means for determining whether an address output from the CPU is within address space allocated to the local variable area in the data cache memory, when the memory read/write access with a stack operation instruction is performed;
- and
- memory read/write access means for accessing the local variable area in the data cache memory means in accordance with a result of the determining means and permanently inhibiting contents of the local variable area from being written into said main memory.
Dependencies are inferred from the claim text.