Error condition detector for handling interrupt in integrated circuits having multiple processors

A method of monitoring for interrupt error conditions in a single integrated circuit on a chip having a plurality of processors incorporated thereon wherein said plurality of processors signal interrupts to others of said plurality of processors on said integrated circuit, said method comprising the steps of:

• routing all interprocessor interrupts to an interrupt processor controller;
• directing interprocessor interrupts from said interrupt processor controller to a destination processor;
• monitoring for an interrupt clear signal from said destination processor;
• detecting when a subsequent interprocessor interrupt to said destination processor will cause an interrupt error condition by:
• determining if a subsequent interrupt for a given interrupt channel is received prior to completion of a previously dispatched interrupt;
• and
• determining if a subsequent interrupt for a given interrupt channel is received simultaneously with a clear signal from a previously dispatched interrupt;
• and
• signaling that said interrupt error condition exists.

A computer system comprising:

• an input/output (I/O) means for providing an communications interface;
• a memory means coupled to said I/O means for storing instructions and computer data;
• data input means coupled to said I/O means for providing data input and data output to interface with a computer user;
• and
• a processing unit coupled to said I/O means for executing instructions and processing computer data, said processing unit being a single integrated circuit on a chip having a plurality of processors embedded thereon wherein each of said plurality of processors signal interrupts to the others of said plurality of processors, said processing unit further incorporating an interrupt error condition detector that comprises:
• an interrupt processor incorporated on said single integrated circuit, said interrupt processor being coupled to communicate with each of said plurality of processors, wherein interprocessor interrupts are routed through said interrupt processor, said interrupt processor detecting any interrupt error conditions between any of said plurality of processors the interrupt processor comprising:
• interrupt routing logic for receiving interprocessor interrupts from each of said plurality of processors and routing them to an appropriate receiving processor, said routing logic being provided with means for detecting interrupt error conditions;
• an error detect register coupled to said interrupt routing logic wherein said interrupt routing logic establishes a logical true bit in said error register when said interrupt rouging logic detects an interrupt error condition;
• and
• means for detecting a logical true bit in said error detect register and providing an active signal on said output signal path in response thereto;
• and
• an output signal path coupled to said interrupt processor for said interrupt processor to signal outside of said chip an interrupt error condition when one is detected by said interrupt processor.

A computer system comprising:

• an input/output (I/O) means for providing a communications interface;
• a memory means coupled to said I/O means for storing instructions and computer data;
• data input means coupled to said I/O means for providing data input and data output to interface with a computer user;
• and
• a processing unit coupled to said I/O means for executing instructions and processing computer data, said processing unit being a single integrated circuit on a chip having a plurality of processors embedded thereon wherein each of said plurality of processors signal interrupts to the others of said plurality of processors, said processing unit further incorporating an interrupt error condition detector that comprises:
• an interrupt processor incorporated on said single integrated circuit, said interrupt processor being coupled to communicate with each of said plurality of processors, wherein interprocessor interrupts are routed through said interrupt processor, said interrupt processor detecting any interrupt error conditions between any of said plurality of processors;
• and
• an output signal path coupled to said interrupt processor for said interrupt processor to signal outside of said chip an interrupt error condition when one is detected by said interrupt processor, wherein the output signal path comprises a pin for conveying an interrupt error condition detect signal out of said integrated circuit.

A computer system comprising:

• an input/output (I/O) means for providing a communications interface;
• a memory means coupled to said I/O means for storing instructions and computer data;
• data input means coupled to said I/O means for providing data input and data output to interface with a computer user;
• and
• a processing unit coupled to said I/O means for executing instructions and processing computer data, said processing unit being a single integrated circuit on a chip having a plurality of processors embedded thereon wherein each of said plurality of processors signal interrupts to the others of said plurality of processors, said processing unit further incorporating an interrupt error condition detector that comprises:
• an interrupt processor incorporated on said single integrated circuit, said interrupt processor being coupled to communicate with each of said plurality of processors, wherein interprocessor interrupts are routed through said interrupt processor, said interrupt processor detecting any interrupt error conditions between any of said plurality of processors;
• an output signal path coupled to said interrupt processor for said interrupt processor to signal outside of said chip an interrupt error condition when one is detected by said interrupt processor;
• and
• means for intercepting an external interrupt destined for one of said plurality of processors and routing said external interrupt to a destined interrupt channel.