Cache tag memory having first and second single-port arrays and a dual-port array
AssigneeSGS-Thomson Microelectronics S.A.
InventorDavid C. McClure
Life of this patent
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Abstract
A cache tag memory device having a memory array comprising a first single-port memory array, a second single-port memory array, and a dual-port memory array. A first port, accessed by a local processor, may read from and write to its corresponding single-port memory array and the dual-port memory array. A second port, accessed through a global system bus, may also read from and write to its corresponding second single-port memory array and the dual-port memory array. Both ports operate asynchronously relative to each other. Status bits indicating the status of the entries in the first and second single-port memory arrays are stored in the dual-port memory array and may be altered by the global system while the local processor is performing its operations.
Claims14
A cache tag memory, comprising:
- a first single-port memory array having a plurality of entries;
- a dual-port memory array having a plurality of entries corresponding to the plurality of entries in the first single-port memory array;
- a second single-port memory array having a plurality of entries corresponding to the plurality of entries in the dual-port memory array and the first single-port memory array;
- a first memory port capable of writing entries to said first single-port memory array said second single-port memory array, and said dual-port memory array, and capable of reading entries from said first single-port memory array and said dual-port memory array;
- means for, when data is written to said dual-port array and said first and second single-port arrays through said first memory port, writing identical data into corresponding entries of said first and second single-port arrays;
- a second memory port capable of reading entries from said second single-port memory array and said dual-port memory array, and capable of writing entries to said dual-port memory array;
- a first comparator connected to said first memory port for comparing an array entry selected by a first portion of a local address with a second portion of the local address, and for generating a signal indicative of a match;
- and
- a second comparator connected to said second memory port for comparing an array entry selected by a first portion of a global address with a second portion of the global address, and for generating a signal indicative of a match.
A cache memory subsystem, comprising:
- a cache tag memory, adapted for connection to a local processor and a system bus, such cache tag memory including a first single-port memory array portion, a second single-port memory array portion, and a dual-port array portion, each of such portions having a plurality of entries;
- a data cache for storing a plurality of entries corresponding to the entries in the first single-port memory array portion, the second single-port memory array portion, and the dual-port array portion;
- a cache controller for controlling exchanges of data or control signals between the local processor and the system bus;
- means for storing, when data is written to said dual-port array portions and said first and second single-port memory array portions through a first port, identical address data corresponding entries of the first and second single-port memory array portions;
- means for reading entries from said second single-port array portion and said dual-port memory array portion and for writing entries to said dual-port memory array portion, through a second port;
- means, connected to the first single-port memory array portion, for generating a first match signal for indicating a memory location addressed by the local processor resides in the data cache;
- means, connected to the dual-port memory array portion, for generating a valid signal for indicating (i) said memory location addressed by the local processor is valid;
- means, connected to the second single-port memory array portion, for generating a second match signal for (ii) indicating a second memory location addressed by the system bus matches an entry in the cache tag memory.
Dependencies are inferred from the claim text.