Watchdog timer for computer system reset
AssigneeDell USA, L.P.
InventorsRichard Finch, Eric Schieve
Life of this patent
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AssigneeDell USA, L.P.
InventorsRichard Finch, Eric Schieve
Estimating the term…
A watchdog timer circuit of the present invention monitors a computer system (S) during diagnostic testing and resets the system when it is nonfunctioning. A real-time clock (RTC) (21), programmed by a central processing unit (CPU) (29) to run for a period of time, produces a reset signal after the period of time elapses. Typically this time period relates to a diagnostic program being run. The reset signal serves as an input to reset circuitry (28) which immediately transmits a nonmaskable interrupt (NMI) to the CPU (29) and, after a delay period, transmits a hardware reset signal to the CPU (29). When functioning properly, the CPU (29) prepares for the hardware reset signal that is produced by the reset circuitry (28) and avoids being reset by the hardware reset signal. However, when the CPU (29) is not functioning properly, the hardware reset signal resets the CPU (29). Additional circuitry stores information regarding where the system (S) failed during the diagnostic testing and retrieves such information for the user upon reset. An additional feature resets all of the components within the system (S) upon a CPU (29) reset via power reset circuitry.
A circuit for resetting a nonfunctioning computer system, comprising:
A method of resetting a nonfunctioning computer system, comprising the steps of:
A circuit for resetting a nonfunctioning computer system, comprising:
A method of resetting a nonfunctioning computer system,
A personal computer, comprising:
A method of diagnosing a personal computer, comprising the steps of:
Dependencies are inferred from the claim text.