Method for built-in self-testing of ring-address FIFOs
AssigneeAT&T Corp.
InventorsAd J. van de Goor, Yervant Zorian
Life of this patent
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Abstract
A dual-port, RAM-type ring-address FIFO (100) is tested by causing the FIFO to execute a composite test method comprised of set of interwoven steps (( 1 )-(31 ) or (1')-(25')). Upon execution, the steps of the composite method cause the FIFO (100) to manifest all possible memory, address and functional faults. The test method manifests faults by causing the FIFO (100) to alter the state of the various flags it normally sets and by altering the logic state of the data normally produced by the FIFO.
Claims12
A method for testing a dual-port, RAM-type ring-address FIFO having a write address and read address registers, comprising the steps of:
- executing a first sequence of operations, including a first set of functional operations and a first read and a first write operation, to detect a first set of functional faults in the FIFO, including faults associated with the ability of the FIFO to read data when none is present in the FIFO, and the ability of the FIFO to acknowledge the occurrence of a read and write operation;
- executing a second sequence of operations, including a re-transmit and reset operations to reset both the write and read address registers simultaneously, and to rest the read address register alone, respectively, to detect a second set of functional faults associated with the ability of the write address and read address registers to be reset;
- executing a third sequence of operations, including second write and read operations, and at least a second functional operation, to detect a third set of functional faults, a first set of memory faults, and a first set of address faults;
- and
- executing a fourth sequence of operations, including third read and write operations, and a third functional operation, to detect a second set of addressing faults, a second set of memory faults and a fourth set of functional faults.
A method for testing a dual-port, RAM-type FIFO having a built-in test pattern generator and a built-in output data evaluator, as well as a built-in test controller for controlling the test pattern generator and the output data evaluator, comprising the steps of:
- executing a first sequence of operations, including a set of functional operations, a first write operation, and a first read operation, to test the ability of the FIFO to read and write data;
- executing a second sequence of operations, including a re-transmit operation, to test the ability of the FIFO to reset itself;
- executing a third sequence of operations, including a sequence of read inhibit and write inhibit operations during which a single location in the FIFO written at least twice prior to writing to another location, to perform a modified march test on the FIFO to detect memory and address faults;
- executing a fourth sequence of operations to detect faults associated with the output data evaluator;
- and
- executing a fifth sequence of operations, including a delay interval, to detect data retention faults.
Dependencies are inferred from the claim text.