Method for generating hierarchical fault-tolerant mesh architectures
AssigneeInternational Business Machines Corporation
InventorsJehoshua Bruck, Robert E. Cypher, Ching-Tien Ho
Life of this patent
Estimating the term…
Loading patent…
AssigneeInternational Business Machines Corporation
InventorsJehoshua Bruck, Robert E. Cypher, Ching-Tien Ho
Estimating the term…
A method is disclosed, for use with a multiprocessing hardware mesh architecture including nodes and a network of interconnections between the nodes, for defining and implementing a target logical mesh architecture utilizing a given subset of the nodes and the interconnections of the hardware architecture. Typically, the hardware mesh architecture includes redundant nodes and interconnections, sot hat the target logical mesh architecture may be defined from the hardware architecture several different ways. As a consequence, the target logical mesh architecture may be defined even in the presence of faulty nodes or interconnections in the hardware architecture. Frequently, the logical mesh is defined in terms of some regular pattern of interconnections. The method of the invention facilitates the definition of the desired logical mesh architecture from the hardware architecture, given the possibility that one or more faults are present, by initially defining logical blocks of nodes from among the functional nodes of the hardware architecture. Then, functional edges between the nodes defined within the logical blocks are defined as logical interconnections between the nodes of the logical blocks, such that the logical blocks, with the interconnections, are structurally consistent with portions of the logical mesh. Finally, additional edges are defined as logical interconnections between nodes in different logical blocks, these additional edges also being consistent with the structure of the logical mesh. The result is that the logical mesh has been fully defined from functional nodes and interconnections in the hardware architecture.
A method for configuring a fault-tolerant target mesh M' from a multiprocessor network, the multiprocessor network having components including a plurality of processor nodes and interconnections therebetween, the components being either healthy or faulty, the multiprocessor network being configured topologically as a d-dimensional fault-tolerant physical mesh M, such that the fault-tolerant target mesh M' is to be configured of healthy components of the multiprocessor network, the method comprising the steps of:
A method for configuring a fault-tolerant target mesh M' from a multiprocessor network, the multiprocessor network having components including a plurality of processor nodes and interconnections therebetween, the components being either healthy or faulty, the multiprocessor network being configured topologically as a d-dimensional fault-tolerant physical mesh M, such that the fault-tolerant target mesh M' is configured of healthy components of the multiprocessor network, the method comprising the steps of:
A multiprocessor network comprising:
A computer program product:
A computer program product for use on a computer system for generating a fault-tolerant target mesh M' from a multiprocessor network, the multiprocessor network having components including a plurality of processor nodes and interconnections therebetween, the components being either healthy or faulty, the multiprocessor network being configured topologically as a d-dimensional fault-tolerant physical mesh M, such that the fault-tolerant target mesh M' is configured of healthy components of the multiprocessor network, the computer program product comprising:
Dependencies are inferred from the claim text.