Non-volatile semiconductor memory device capable of checking the threshold value of memory cells

A non-volatile semiconductor memory device comprising:

• a plurality of memory cells each for storing data by a change in a threshold value;
• write means, connected to said plurality of memory cells, for writing predetermined data in a selected memory cell by setting the threshold value of said selected memory cell higher than a predetermined value;
• erasing means, connected to said plurality of memory cells, for electrically erasing said plurality of memory cells;
• and
• means for discriminating said memory device as a defect by detecting, as an electrically over-erased memory cell, any and all memory cells which will become improperly conductive by parasitic capacitance between a drain of said memory cell and said .gate during normal read or write cycles, said discriminating means comprising:
• checking means, connected to said plurality of memory cells, for checking if the threshold values of those memory cells electrically erased by said erasing means are equal to or greater than a predetermined reference value which is a positive voltage less than a power source voltage and substantially equal to a minimum normal operating threshold value of those of said memory cells which are electrically erased.

A memory cell checking method comprising:

• an erasing step of electrically erasing a plurality of memory cells of a memory chip;
• a checking step of checking if threshold values of said memory cells are equal to or above a reference value to detect an electrically over-erased memory cell, said checking step being performed after completion of said erasing step;
• and
• a step of discriminating said memory chip as a defect when a memory cell whose threshold value is below said reference value, which is a positive voltage less than a power source voltage and substantially equal to a minimum normal operating threshold value of those of said memory cells which are electrically erased, is detected in said checking step.

A memory cell checking method comprising:

• a writing step for writing data in a plurality of memory cells to be electrically erased, to set a threshold value of each of said memory cells equal to or greater than a predetermined value, said plurality of memory cells being included in a memory chip and storing data by changing the threshold values;
• an erasing step of electrically erasing said plurality of memory cells to be erased to which data are electrically written by said writing step;
• an erase verify step for checking the threshold values of said electrically erased memory cells and repeating said erasing step until the threshold value of all of said plurality of memory cells to be erased become equal to or below a first positive value;
• a checking step to be performed after detecting that said threshold value of all of said plurality of memory cells to be erased have become equal to or below said first positive value, to check if the threshold values of said plurality of memory cells are equal to or above a second positive value substantially equal to a minimum normal operating threshold value of those of said memory cells which are electrically erased and smaller than the first positive value to detect an electrically over-erased memory cell;
• and
• a step of discriminating said memory chip as a defect when a memory cell whose threshold value is below said second positive value is detected as electrically over-erased in said checking step.

A memory cell checking method comprising the steps of:

• providing an electrically erasable and programmable non-volatile semiconductor memory device which includes a plurality of MOS transistor memory cells each having a source, a drain, a control gate and a floating gate, the control gate of each of said MOS transistor memory cells being connected to an associated one of address lines and the drain of each of said MOS transistor memory cells being connected in common to a digit line, one of said MOS transistor memory cells being in a data-write operation supplied with a set of writing voltages through an associated one of said address lines and said digit line while applying a first voltage to the control gate of each of remaining ones of said MOS transistor memory cells through remaining ones of said address lines, said one of said MOS transistor memory cells being thereby changed to have a first threshold value higher than a predetermined threshold value, and each of said remaining ones of said MOS transistor memory cells thereby receiving a second voltage at the floating gate thereof due to capacitance-coupling between the drain and the floating gate, said second voltage being higher than said first voltage;
• writing a data into each of said MOS transistor memory cells by supplying said set of writing voltages thereto, each of said MOS transistor memory cells being thereby changed to have said first threshold value;
• performing an erasing-verifying operation in which each of said MOS transistor memory cells is applied with a set of erasing voltages, simultaneously, for a predetermined time period, and each of said MOS transistor memory cells is then supplied with a set of verifying voltages to check if all said MOS transistor memory cells have a second threshold value smaller than said predetermined threshold value, said erasing-verifying operation being repeated until all the MOS transistor memory cells have said second threshold value;
• and
• supplying a third voltage that is substantially equal to said second voltage to the control gate of each of said MOS transistor memory cells through an associated one of said address line to thereby check if said MOS transistor memory cell is made conductive by said third voltage.