Enhanced interconnect testing through utilization of board topology data
AssigneeHewlett-Packard Company
InventorsKenneth P. Parker, Kenneth E. Posse
Life of this patent
Estimating the term…
Abstract
A method for generating improved detection and diagnostic test patterns and for improving the diagnostic resolution of interconnect testing of a circuit is based on the premise that short-circuits are most likely to result from solder bridges between closely adjacent pins. In a first embodiment, an optimal boundary-scan test pattern is generated. In a second embodiment, boundary-scan test diagnosis is enhanced by utilizing x,y coordinate data corresponding to the physical location of devices on the tested circuit. In a third embodiment, diagnosis of unpowered short-circuit testing is enhanced.
Claims20
An automated method for increasing the diagnostic resolution of a boundary-scan interconnect test performed on a circuit, wherein the circuit includes a plurality of integrated circuit chips, each integrated circuit chip having a plurality of I/O pins, the I/O pins making electrical interconnection through a plurality of independent conductive nets, said method comprising:
- (1) receiving a list of net signatures generated during execution of a boundary-scan interconnect test;
- (2) grouping together nets having identical net signatures into groups of potentially shorted nets;
- (3) examining x,y coordinate data contained in a board physical description of the circuit to identify radial adjacencies between I/O pins in the circuit;
- and
- (4) for each group of potentially shorted nets, determining which nets are likely short-circuited together based on said radial adjacencies between I/O pins of said nets in said group of potentially shorted nets.
An automated method for performing boundary-scan interconnect testing of a circuit, wherein the circuit includes a plurality of integrated circuit chips, each integrated circuit chip having a plurality of I/O pins, the I/O pins making electrical interconnection through a plurality of independent conductive nets, said method comprising:
- (1) serially scanning a test vector into the circuit through a scanpath;
- (2) broadcasting said test vector from a plurality of output buffers in the circuit over said conductive nets;
- (3) capturing said test vector into a plurality of receiving register cells in the circuit;
- (4) serially scanning said test vector out of the receiving register cells via said scanpath;
- (5) repeating steps (1) through (4) for a plurality of test vectors;
- (6) producing a plurality of net signatures from said plurality of captured test vectors;
- (7) grouping together nets having identical net signatures into a group of potentially shorted nets;
- (8) examining x,y coordinate data contained in a board physical description of the circuit to identity radial adjacencies between I/O pins in the circuit;
- and
- (9) for each group of potentially shorted nets, determining which nets are likely short-circuited together based on said radial adjacencies between I/O pins of said nets in said group of potentially shorted nets.
A method for generating detection and diagnostic test patterns for boundary-scan interconnect testing of a circuit, wherein the circuit includes a plurality of integrated circuit chips, each integrated circuit chip having a plurality of I/O pins, the I/O pins making electrical interconnection through a plurality of independent conductive nets, said method comprising:.
- (1) grouping together conductive nets which have radially adjacent I/O pins;
- (2) assigning a unique net identification number to each conductive net in a group according to a high diagnostic test pattern, wherein said unique net identification numbers are duplicated between said groups, and wherein conductive nets which are common to more than one group receive only a single unique net identification number;
- (3) assigning a unique group identification number to each group according to a brief test pattern;
- (4) appending said group identification number for each group to said net identification number for each conductive net in said each group to form a unique net identifier for each conductive net;
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- (5) combining said net identifiers to form a matrix, wherein each row of the matrix is one of said net identifiers, and wherein each column of the matrix is a unique test vector available for boundary scan testing.
A method for generating detection and diagnostic test patterns for boundary-scan interconnect testing of a circuit, wherein the circuit includes a plurality of integrated circuit chips, each integrated circuit chip having a plurality of I/O pins, the I/O pins making electrical interconnection through a plurality of independent conductive nets, said method comprising:
- (1) receiving logical interconnect data defining the logical interconnection between the integrated circuit chips in the circuit;
- (2) receiving I/O pin coordinate data for the I/O pins of the integrated circuit chips in the circuit;
- (3) receiving a predetermined a radial distance within which improper interconnections between adjacent I/O pins may occur during manufacture of the circuit, said radial distance defining a radial adjacency;
- (4) analyzing each I/O pin in a conductive net for radial adjacency to I/O pins of other conductive nets;
- (5) grouping together conductive nets which have radially adjacent I/O pins;
- (6) assigning a unique net identification number to each conductive net in a group according to a high diagnostic test pattern, wherein said unique net identification numbers are duplicated between said groups, and wherein conductive nets which are common to more than one group receive only a single unique net identification number;
- (7) assigning a unique group identification number to each group according to a brief test pattern;
- (8) appending said group identification number for each group to said net identification number for each conductive net in said each group to form a unique net identifier for each conductive net;
- and
- (9) combining said net identifiers to form a matrix, wherein each row of the matrix is one of said net identifiers, and wherein each column of the matrix is a unique test vector available for boundary scan testing.
A method for performing boundary-scan interconnect testing of a circuit, wherein the circuit includes a plurality of integrated circuit chips, each integrated circuit chip having a plurality of I/O pins, the I/O pins making electrical interconnection through a plurality of independent conductive nets, said method comprising:
- (1) grouping together conductive nets which have radially adjacent I/O pins;
- (2) assigning a unique net identification number to each conductive net in a group according to a high diagnostic test pattern, wherein said unique net identification numbers are duplicated between said groups, and wherein conductive nets which are common to more than one group receive only a single unique net identification number;
- (3) assigning a unique group identification number to each group according to a brief test pattern;
- (4) appending said group identification number for each group to said net identification number for each conductive net in said each group to form a unique net identifier for each conductive net;
- (5) combining said net identifiers to form a matrix, wherein each row of the matrix is one of said net identifiers, and wherein each column of the matrix is a unique test vector available for boundary scan testing;
- (6) serially scanning a selected test vector into the circuit through a scanpath;
- (7) broadcasting said selected test vector from a plurality of output buffers in the circuit over said conductive nets;
- (8) capturing said selected test vector broadcast over said conductive nets into a plurality of receiving register cells in the circuit;
- (9) serially scanning said selected test vector captured into said plurality of receiving register cells out of the circuit through said scanpath;
- (10) comparing said selected test vector scanned out of the circuit with said selected test vector serially scanned into the circuit;
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- (11) repeating steps (6) through (10) for each test vector in said matrix.
An automated method for performing an interconnect test on a circuit board having a plurality of integrated circuit chips, each integrated circuit chip having a plurality of I/O pins, the I/O pins making electrical interconnection through a plurality of independent conductive nets, the method comprising:
- (1) simultaneously contacting each of the plurality of nets on the circuit board with one of a plurality of test probes;
- (2) applying a first potential to a selected one of the plurality of nets via a corresponding test probe;
- (3) applying a second potential to all remaining ones of the plurality of nets via said plurality of test probes;
- (4) monitoring a current flow through said corresponding test probe;
- (5) if said current flow exceeds a threshold, indicating a short-circuit for said selected one of the plurality of nets;
- (6) examining x,y coordinate data contained in a board physical description of the circuit to identify radial adjacencies between I/O pins in the circuit:
- and
- (7) determining probable locations of said short-circuit based on said radial adjacencies between I/O pins of said selected one of the plurality of nets and I/O pins of all remaining ones of the plurality of nets.
An automated method for facilitating location of a short-circuit fault between a plurality of nets on a circuit board after the presence of the short-circuit fault has been indicated by a test, the method comprising the steps of:
- (a) examining x,y coordinate data contained in a physical description of the circuit board to generate an adjacency list that identifies radial adjacencies between I/O pins on the circuit board;
- (b) identifying, from said adjacency list, all radially adjacent I/O pins of said plurality of nets, wherein a radially adjacent I/O pin is an I/O pin of one of the plurality of nets which is radially adjacent to an I/O pin of another of the plurality of nets;
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- (b) indicating a physical location of a radially adjacent I/O pin as a probable location of said short-circuit.
An automated method for increasing the diagnostic resolution of a boundary-scan interconnect test performed on a circuit board, wherein the circuit board includes a plurality of conductive nets, each of the plurality of conductive nets connecting a plurality of circuit devices at physical connection points defined by x,y coordinates, the method comprising the steps of:
- (1) receiving a list of nets identified by the boundary-scan interconnect test as a group of potentially shorted nets, wherein each of the nets in said group of potentially shorted nets has identical net signatures;
- (2) determining whether the x,y coordinates of any one of the physical connection points on a single net in said group of potentionally shorted nets is within a defined radial proximity of the x,y coordinates of any one of the physical connection points on any of the remaining nets in said group of potentionally shorted nets;
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- (3) grouping together those nets in said group of potentionally shorted nets that have physical connection points within said defined radial proximity.
An automated method for facilitating location of a short-circuit fault between a suspect group of nets on a circuit board after the presence of the short-circuit fault has been indicated by a test, wherein the circuit board includes a plurality of conductive nets, each of the plurality of conductive nets connecting a plurality of circuit devices at physical connection points defined by x,y coordinates, the method comprising the steps of:
- (1) for each net in the suspect group of nets, determining a list of x,y coordinates that includes the x,y coordinates of all physical connection points that are within a defined radial proximity to a physical connection point on another net in the suspect group of nets;
- and
- (2) providing a listing of I/O pin locations, corresponding to said list of x,y coordinates, to assist a technician in physically locating short-circuit faults.
Dependencies are inferred from the claim text.