Synchronous NAND DRAM architecture

An integrated circuit memory device comprising:

• a) a clock node for receiving a clock signal;
• b) an address latch, a data latch and a control latch, each connected to said clock node for latching an address signal, a data signal and control signals respectively in response to transitions of the clock signal;
• c) an output latch connected to said clock node;
• d) a first and second plurality of word lines;
• e) a first bank of NAND structured memory cells connected to said first plurality of word lines and connected to a first bit line;
• f) a second bank of NAND structured memory cells connected to said second plurality of word lines and connected to a second bit line;
• g) a first word line activation circuit connected to said control latch, said address latch and said first plurality of word lines, responsive to the control signals, the address signal and the clock signal for activating a sequence of said first plurality of word lines;
• h) a second word line activation circuit connected to said control latch, said address latch and said second plurality of word lines, responsive to the control signals, the address signal and the clock signal for activating a sequence of said second plurality of word lines;
• i) a first plurality of random access storage registers connected to said first bit line, said data latch, said address latch and said output latch;
• and
• j) a second plurality of random access storage registers connected to said second bit line, said data latch, said address latch and said output latch.

A memory device for storing data, comprising:

• a) a clock node for receiving a clock signal;
• b) an array of serial access memory elements, the array having a first and a second dimension, each of the elements having a plurality of storage cell access devices connected in series;
• c) a plurality of word lines, each word line connected to one of the plurality of storage access devices in each of the serial access memory elements along the first dimension of said array;
• d) a plurality of bit lines, one bit line of said plurality of bit lines for each of the serial access memory elements along the first dimension of said array connected to each serial access memory element along the second dimension of said array;
• e) a two port data register comprising a serial port connected to said array, and a random access port;
• and
• f) a data latch connected to an external access point of the memory device and to the random access port of said two port data register, wherein said data latch latches the data from said two port data register into said data latch in synchronization with the clock signal.

A method for high speed access of data within a memory device having an array of NAND structured memory cells and input nodes for receiving a clock signal, control signals and address signals, the method comprising:

• a) activating a series of word lines of the array whereby a plurality of data bits from a NAND structured memory cell are sequentially transferred onto a bit line;
• b) storing the plurality of data bits in a storage register;
• c) accessing a first data bit of the plurality of data bits from the storage register in response to the clock signal, the control signals and the address signals;
• d) advancing an address counter in response to the clock signal to access a second data bit;
• e) accessing a second data bit of the plurality of data bits from the storage register;
• f) transferring the plurality of data bits from the storage register onto the bit line;
• and
• g) deactivating the series of word lines of the array of memory cells.

A method for high speed access of data within a memory device having first and second banks of NAND structured memory cells and input nodes for receiving a clock signal, control signals and address signals, the method comprising:

• a) activating a first series of word lines of the first bank of NAND structured memory cells;
• b) accessing a first data word from the first bank of NAND structured memory cells in response to the clock, control and address signals;
• c) advancing an address counter;
• d) accessing a second data word from the first bank of NAND structured memory cells;
• e) activating a second series of word lines of the second bank of NAND structured memory cells while data from the first bank of NAND structured memory cells is being accessed;
• and
• f) accessing a third data word from the second bank of NAND structured memory cells in response to the clock, control and address signals.