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US 5,513,147 AGranted
Row driving circuit for memory devices
AssigneeAlliance Semiconductor Corporation
InventorBruce L. Prickett, Jr.
Life of this patent
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AssigneeAlliance Semiconductor Corporation
InventorBruce L. Prickett, Jr.
Estimating the term…
A row driving circuit (10) having a reduced number of transistors provides range of row deselect voltages, and eliminates the need for an NMOS pull-down device. The row driving circuit (10) has a-level shifter (14) formed by a PMOS input pull transistor P1 that is drain coupled at node V 10 to an NMOS input transistor N1. N1 functions as passgate for a row select signal and inverted row select signal applied to its gate and source respectively. A PMOS row pull-up transistor P2 has its gate coupled to V 10, its source coupled to a variable positive supply voltage (12), and its drain coupled to the source of a PMOS row select transistor P3. The drain and gate of P3 are coupled to switching circuits S 11 and S 12 respectively. S 11 and S 12 provide gate and drain voltages to quickly deselect the row by pulling the row to a negative deselect voltage. A PMOS erase transistor is also source coupled to the row with its gate coupled to switching circuit S 13 and its drain coupled to switching circuit S14. S13 and S14 provide a negative erase voltage to both the gate and drain of P4. In addition, S13 and S 14 can bias P4 into linear mode, allowing P4 to operate a leaker transistor, pulling the row down to a deselect voltage.
In an integrated circuit having at least one row of memory cells, a row driving circuit for selecting and deselecting a row, comprising:
A row driving circuit for driving a row in a memory array, comprising:
A row driving circuit for driving a row in a memory array, comprising:
In a row driving circuit having an NMOS passgate input transistor for receiving row select signals, a PMOS input pull-up transistor drain coupled to the NMOS transistor, a PMOS row pull-up transistor coupled by its gate to the drains of the NMOS passgate and the PMOS input pull-up transistors, by its source to a variable positive supply voltage, and by its drain to the row, and a PMOS erase transistor that is source coupled to the row, the improvement comprising:
Dependencies are inferred from the claim text.