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US 5,513,146 AGranted
Nonvolatile semiconductor memory device having a row decoder supplying a negative potential to word lines during erase mode
AssigneeKabushiki Kaisha Toshiba
InventorsShigeru Atsumi, Sumio Tanaka
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Abstract
A nonvolatile semiconductor memory device is provided in which a negative voltage is applied to a gate electrode of a memory cell transistor during an erase mode. The memory device includes a row decoder circuit having an N-channel transistor connected to a word line. The N-channel transistor is provided on a P-type well region of a semiconductor substrate. A negative voltage is applied to the P-type well region during the erase mode, while ground potential is applied thereto during other modes.
Claims17
A nonvolatile semiconductor memory device, comprising:
- a memory cell array having a plurality of memory cells arranged in a row and column matrix;
- first and second word lines each connected to the memory cells in a respective corresponding row of said matrix;
- a negative charge pump circuit for generating a negative potential;
- and
- a row decoder circuit, connected to said first and second word lines and said negative charge pump circuit, for applying the negative potential to said first and second word lines, comprising:
- an address decoding circuit connected between a first power supply terminal and a second power supply terminal, said address decoding circuit receiving a plurality of row select signals and generating a selection signal at an output node thereof;
- and
- a driver circuit including a first and second transistors each having a source, a drain, a gate and a substrate node, said drain of sad first transistor being connected to said first word line, said drain of said second transistor being connected to said second word line, said sources of said first and second transistors being commonly connected to said negative charge pump circuit, said gates of said first and second transistors being commonly connected to said output node of said address decoding circuit, and said substrate nodes of said first and second transistors being connected to said negative charge pump circuit.
5 more elements
A nonvolatile semiconductor memory device, comprising:
- a memory cell array having a plurality of memory cells arranged in a row and column matrix;
- a plurality of word lines each connected to the memory cells in a respective corresponding row of said matrix;
- a decoder circuit, connected between a first power supply terminal and a voltage V.sub.ss, for decoding a select signal;
- an inverter circuit, connected between second and third power supply terminals, for inverting an output signal of said decoder circuit;
- a circuit having an output which constitutes said third power supply terminal;
- a transfer circuit for transferring word lit e select signals to said word lines said inverter circuit is connected between said decoder circuit and said transfer circuit;
- and
- discharging means, connected between said word lines and said third power supply terminal, for discharging said word lines,
- wherein, in a read mode, said first power supply terminal is set to a voltage V.sub.cc, said second power supply terminal is set to a voltage V.sub.cc, and said third power supply terminal is set to the voltage V.sub.ss,
- wherein, in a write mode, said first power supply terminal is set to a voltage V.sub.pp, said second power supply terminal is set to the voltage V.sub.pp, and said third power supply terminal is set to the voltage V.sub.ss,
- wherein, in an erase mode, said first power supply terminal is set to the voltage V.sub.cc, said second power supply terminal is set to the voltage V.sub.ss, and said third power supply terminal is set to a voltage V.sub.bb, and
- wherein V.sub.pp >
- V.sub.cc >
- V.sub.ss >
- V.sub.bb.
12 more elements
Dependencies are inferred from the claim text.