FIFO memory device capable of writing contiguous data into rows

A FIFO synchronizing device for adjusting timing of data input to a current unit from a preceding unit at a preceding stage, said FIFO synchronizing device comprising:

• FIFO memory means where the data input from the preceding unit is written and then read out in a first-in first-out manner, wherein write cycles of said FIFO memory means start in synchronization with a first synchronizing signal in said current unit and read cycles of said FIFO memory means start in synchronization with a second synchronizing signal provided from said preceding unit;
• write counting means coupled to said FIFO memory means for counting write cycles of said FIFO memory means to obtain a write data count;
• read counting means coupled to said FIFO memory means for counting read cycles of said FIFO memory means to obtain a read data count;
• and
• synchronizing signal output means, coupled to said write counting means and said read counting means, for outputting a third synchronizing signal to said preceding unit which is generated therein based on the second synchronizing signal with timing adjustment according to a difference between the write data count and the read data count.