Data cache memory internal circuitry for reducing wait states

Abstract

The mechanism for performing writes to the data cache memory in a cache subsystem is modified to reduce the occurrence of microprocessor wait states. Concurrently, with operation of the tag RAM, the write signal from the microprocessor propagates through the data cache up to a point in the internal circuitry of the data cache which is as close as reasonably possible to the memory cell being written. At this point in the circuitry, the write signal is gated by the Match signal from the tag RAM. Address decoding is completed prior to receiving the Match signal, such that when the tag RAM generates a "hit" Match output signal, the write signal is allowed to finish propagating through data cache internal circuitry without additional address set-up time. This allows the memory cell to be written to quickly and reduces the probability of microprocessor wait states. In a preferred embodiment of the present invention, the write signal propagates to a logic function, such as a logic gate, where it is gated by the Match signal from the tag RAM and data. When the tag RAM generates a "hit" Match output signal, the write signal as well as the data is allowed to finish propagating to the memory cell.

Dependencies are inferred from the claim text.