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US 5,513,142 AGranted
Semiconductor memory device for maintaining level of signal line
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsKazutami Arimoto, Shigeki Tomishima, Hideto Hidaka
Life of this patent
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Abstract
A memory array MA.sub.0 is divided into four sub memory arrays by sense amplifier strips. Word drivers belonging to each sub memory array are connected to a corresponding segment boosted signal line. A fuse is connected to each segment boosted signal line. By blowing out a fuse, the sub memory array corresponding to the blown out fuse is no longer used. The sub memory array that is no longer used is exchanged with a spare sub memory array of a spare memory array.
Claims41
A semiconductor memory device comprising:
- a submemory array having a plurality of memory cells connected to a plurality of word lines,
- a global boosted line to which a boosted potential higher than a power supply potential is supplied,
- a segment boosted line provided corresponding to said submemory array,
- word line select means for selecting any of said plurality of word lines,
- word line activation means responsive to an output from said word line select means for providing the potential of said segment boosted line to a selected one of said plurality of word lines to activate the same,
- first switching means connected between said segment boosted line and said global boosted line for selecting an electrical connection of said segment boosted line with said global boosted line, and
- potential maintaining means for maintaining the potential of said segment boosted line at a potential between ground potential and said boosted potential provided to said global boosted line.
4 more elements
A semiconductor memory device comprising:
- a memory array having a plurality of submemory cells connected to a plurality of word lines,
- a global boosted line to which a boosted potential higher than a power supply potential is supplied,
- a segment boosted line provided corresponding to said submemory array,
- a row decoder for selecting any of said plurality of word lines,
- a plurality of word drivers, each connected between said segment boosted line and each of said plurality of word lines,
- wherein each of said plurality of word drivers comprises
- a first conductivity type transistor connected between said segment boosted line and a word line corresponding to each of said plurality of word drivers, and having a control electrode supplied with an output of said row decoder,
- a second conductivity type transistor having a first electrode connected to said corresponding word line, a second electrode supplied with ground potential, and a control electrode supplied with an output of said row decoder,
- a switching transistor connected between said segment boosted line and said global boosted line for being turned on/off according to a control signal applied to the control electrode thereof,
- control signal generating means for generating a control signal applied to the control electrode of said switching transistor, and
- potential maintaining means for maintaining the potential of said segment boosted line at a potential between ground potential and said boosted potential applied to said global boosted line.
8 more elements
A semiconductor memory device comprising a word line activation means for activating a word line, wherein said word line activation means comprises
- a first, first conductivity type transistor having a control electrode applied with a row decode signal, and a first electrode supplied with a boosted decode signal, and
- a second conductivity type transistor having a control electrode supplied with a row decode signal identical to said row decoder signal, and connected in series with said first first conductivity type transistor.
A semiconductor memory device comprising a word driver for activating a word line, wherein said word driver comprises
- a first p channel MOS transistor having a gate electrode supplied with a row decode signal and a source electrode supplied with a boosted decode signal, and
- an n channel MOS transistor having a gate electrode supplied with a row decode signal identical to said row decode signal, and connected in series with said first p channel MOS transistor.
A semiconductor memory device comprising a submemory array having a plurality of memory cells connected to a plurality of word lines, wherein said submemory array comprises a plurality of memory cell groups, each of said plurality of memory cell groups including a predetermined number of said plurality of word lines
- a plurality of segment boosted lines each provided corresponding to each memory cell group, to which a boosted potential higher than a power supply potential is selectively applied,
- word line select means for selecting any of said plurality of word lines, and
- word line activation means responsive to an output of said word line select means for providing the potential of the segment boosted line to which said boosted potential is selectively applied to any of said predetermined number of word lines included in each memory cell group for activating the same.
A semiconductor memory device comprising:
- a submemory array having a plurality of memory cells connected to a plurality of word lines,
- wherein said submemory array comprises a plurality of memory cell groups, each of said plurality of memory cell groups including a predetermined number of said plurality of word lines,
- a spare memory array having a plurality of spare memory cells connected to a plurality of spare word lines,
- wherein said spare memory array comprises a spare memory cell group, said spare memory cell group including a predetermined number of said plurality of spare word lines,
- a global boosted line to which a boosted potential higher than a power supply potential is supplied,
- a plurality of segment boosted lines each provided corresponding to each of said plurality of memory cell groups,
- a spare segment boosted line provided corresponding to said spare memory cell group,
- a row decoder for selecting any of said plurality of word lines,
- a spare row decoder for selecting any of said plurality of spare word lines,
- a plurality of first switching transistors, each connected between each of said plurality of segment boosted lines and said global boosted line, for selecting an electrical connection of each of said plurality of segment boosted lines with said global boosted line,
- a second switching transistor connected between said spare segment boosted line and said global boosted line for selecting an electrical connection of said spare segment boosted line with said global boosted line,
- a plurality of word drivers, each connected between each of said plurality of segment boosted lines and said plurality of word lines for transmitting the potential of a segment boosted line connected to said global boosted line according to an output of said row decoder to any of said predetermined number of word lines included in each memory cell group,
- a plurality of spare word drivers, each connected between said spare segment boosted line and each of said plurality of spare word lines, for transmitting the potential of a spare segment boosted line connected to said global boosted line according to an output of said spare row decoder to any of said predetermined number of spare word lines included in a corresponding spare memory cell group, and
- a plurality of fuses provided corresponding to each of said plurality of first switching transistors to be programmed to always turn off each of said plurality of first switching transistors.
11 more elements
A semiconductor memory device comprising:
- a submemory array having a plurality of memory cells connected to a plurality of word lines,
- wherein said submemory array comprises a plurality of memory cell groups, each of said plurality of memory cell groups including a predetermined number of said plurality of word lines,
- a spare memory array having a plurality of spare memory cells connected to a plurality of spare word lines,
- wherein said spare memory array comprises a spare memory cell group, said spare memory cell group including a predetermined number of said plurality of spare word lines,
- a global boosted line to which a boosted potential higher than a power supply potential is supplied,
- a plurality of segment boosted lines each provided corresponding to each of said plurality of memory cell groups,
- a spare segment boosted line provided corresponding to said spare memory cell group,
- a row decoder for selecting any of said plurality of word lines,
- a spare row decoder for selecting any of said plurality of spare word lines,
- a plurality of first switching transistors, each connected between each of said plurality of segment boosted lines and said global boosted line, for selecting an electrical connection of each of said plurality of segment boosted lines with said global boosted line,
- a second switching transistor connected between said spare segment boosted line and said global boosted line for selecting an electrical connection of said spare segment boosted line with said global boosted line,
- a plurality of word drivers, each connected between each of said plurality of segment boosted lines and said plurality of word lines for transmitting the potential of a segment boosted line connected to said global boosted line according to an output of said row decoder to any of said predetermined number of word lines included in each corresponding memory cell group,
- a plurality of spare word drivers, each connected between said spare segment boosted line and each of said plurality of spare word lines, for transmitting the potential of a spare segment boosted line connected to said global boosted line according to an output of said spare row decoder to any of said predetermined number of spare word lines included in a corresponding spare memory cell group, and
- a plurality of fuses, each provided between said global boosted line and each of said plurality of segment boosted lines, connected in series with each of said plurality of first switching transistors.
11 more elements
A semiconductor memory device comprising:
- a submemory array having a plurality of memory cells connected to a plurality of word lines;
- a global boosted line to which a boosted potential higher than a power supply potential is supplied;
- a segment boosted line provided corresponding to said submemory array;
- word line select means for selecting any of said plurality of word lines;
- word line activation means responsive to an output from said word line select means for providing the potential of said segment boosted line to a selected one of said plurality of word lines to activate the same;
- and
- switching means connected between said segment boosted line and said global boosted line for selecting an electrical connection of said segment boosted line with said global boosted line, wherein
- said switching means is conductive in an active cycle of said submemory array, and is non-conductive in a standby cycle of said submemory array.
5 more elements
A semiconductor memory device comprising:
- a submemory array having a plurality of memory cells connected to a plurality of word lines;
- a global boosted line to which a boosted potential higher than a power supply potential is supplied;
- a segment boosted line provided corresponding to said submemory array;
- word line select means for selecting any of said plurality of word lines;
- a plurality of word drivers responsive to an output from said word line select means for providing the potential of said segment boosted line to a selected one of said plurality of word lines to activate the same,
- wherein each of said plurality of word drivers is connected between said segment boosted line and each of said plurality of word lines, and wherein each of said plurality of word drivers comprises,
- a first conductivity type transistor connected between said segment boosted line and a word line corresponding to each of said plurality of word drivers, and having a control electrode supplied with an output of said word line selecting means, and
- a second conductivity type transistor having a first electrode connected to said corresponding word line, a second electrode supplied with ground potential, and a control electrode supplied with an output of said word line selecting means;
- and
- a switching means connected between said segment boosted line and said global boosted line for selecting an electrical connection of said segment boosted line with said global boosted line, wherein
- said switching means is conductive in an active cycle of said submemory array, and is non-conductive in a standby cycle of said submemory array.
8 more elements
A semiconductor memory device comprising:
- a submemory array having a plurality of memory cells connected to a plurality of word lines;
- a global boosted line to which a boosted potential higher than a power supply potential is supplied;
- a segment boosted line provided corresponding to said submemory array;
- word line select means for selecting any of said plurality of word lines;
- a plurality of CMOS word drivers responsive to an output from said word line select means for providing the potential of said segment boosted line to a selected one of said plurality of word lines to activate the same,
- wherein each of said plurality of CMOS word drivers is connected between said segment boosted line and each of said plurality of word lines, and wherein each of said plurality of CMOS word drivers comprises,
- a first conductivity type transistor connected between said segment boosted line and a word line corresponding to each of said plurality of word drivers, and having a control electrode supplied with an output of said word line selecting means, and
- a second conductivity type transistor having a first electrode connected to said corresponding word line, a second electrode supplied with ground potential, and a control electrode supplied with an output of said word line selecting means;
- switching means connected between said segment boosted line and said global boosted line for selecting an electrical connection of said segment boosted line with said global boosted line, wherein
- said switching means is conductive in an active cycle of said submemory array, and is non-conductive is a standby cycle of said submemory array;
- and
- potential maintaining means for maintaining the potential of said segment boosted line at a potential between ground potential and said boosted potential provided to said global boosted line.
9 more elements
A semiconductor memory device comprising:
- a memory array including a plurality of submemory arrays, each submemory array having a plurality of memory cells arranged in rows and columns and a plurality of word lines arranged in the corresponding rows;
- a plurality of segment boosted lines, each provided corresponding to each submemory array, respectively, to which a boosted potential higher than a power supply potential is selectively applied,
- a plurality of row decoders, each provided corresponding to each submemory array, respectively, and for selecting any of said plurality of word lines arranged in the corresponding submemory array, and
- a plurality of word driver groups each provided corresponding to each submemory array, respectively, each word driver group including a plurality of word drivers, each word driver provided corresponding to each word line of the corresponding sub memory array and responsive to an output of the corresponding row decoder for applying the boosted potential of the corresponding segment boosted line to the corresponding word line of the corresponding submemory array.
1 more element
Dependencies are inferred from the claim text.