Single port register
AssigneeAT&T Corp.
InventorGlen E. Offord
Life of this patent
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Abstract
A novel mad/write control register uses the same bus port for reading and writing, while requiting only one unique control line. The technique may be implemented as a "D" type level sense latch. The write operation is similar to standard latch operation: the transmission gate on the D input is turned on while the feedback transmission gate is off. However, for read operation, both transmission gates are enabled, thereby allowing the register output value to drive the bus. A preset or clear capability may optionally be provided. This approach reduces the size of the register as compared to standard read/write registers, and requires only one unique control line versus two, thus reducing decoding logic and routing. Since only one port to the bus is required, the bus load gate capacitance is typically one-half that of the standard approach.
Claims5
An integrated circuit having a data register that communicates with a read/write data bus, said register having a write input and an address input, and having a register output for providing a register output signal;
- wherein said data register provides a signal on said data bus to said register output when a write signal is supplied to said write input and an address signal is supplied to said address input, and further provides said register output signal to said data bus when said address signal is supplied to said address input and said write signal is not supplied to said write input;
- and wherein the data register holds its present value when an address signal is not supplied to said address input.
Dependencies are inferred from the claim text.