Data output buffer

For use in a semiconductor circuit device, an output buffer responsive to a control signal generated in the semiconductor circuit device, the output buffer comprising:

• a power supply signal providing at least one voltage level with respect to common;
• an output terminal;
• a pull-up node;
• a circuit responding to the control signal by providing a control voltage on the pull-up node;
• a pull-up circuit, responsive to the voltage on the pull-up node and coupled between the power supply signal and the output terminal;
• a bias circuit, responsive to a voltage level on the output terminal being at a level substantially below common, constructed and arranged to bias the pull-up node downwardly and away from the voltage level provided by the power supply signal;
• a disable circuit, responsive to the voltage level on the output terminal being at a level substantially below common, constructed and arranged to disable the circuit providing the control voltage on the pull-up node.

For use in a semiconductor circuit device, a tri-state output buffer responsive to a control signal generated in the semiconductor circuit device, the output buffer comprising:

• a power supply signal providing at least one voltage level with respect to common;
• an output terminal;
• a pull-up node;
• a pull-down node;
• a first circuit responding to the control signal by providing a first control voltage on the pull-up node;
• a second circuit responding to the control signal by providing a second control voltage on the pull-down node;
• a pull-up transistor, responsive to the voltage on the pull-up node and coupled between the power supply signal and the output terminal;
• a pull-down transistor, responsive to the voltage on the pull-down node and coupled between common and the output terminal;
• a bias circuit, responsive to a voltage level on the output terminal being at a level substantially below common, constructed and arranged to bias the pull-up node downwardly and away from the voltage level provided by the power supply signal;
• and
• a disable circuit, responsive to the voltage level on the output terminal being at a level substantially below common, constructed and arranged to disable the circuit providing the control voltage on the pull-up node;
• wherein the pull-up transistor provides a high-level signal at the output terminal, the pull-down transistor provides a low-level signal at the output terminal, and the bias circuit in combination with the disable circuit respond to the voltage level on the output terminal being at a level substantially below common by preventing current flow from the power supply signal to the output terminal.