US 5,513,139 A · Random access memory with circuitry for concurrently and sequentially writing-in and reading-out data at different rates

Abstract

A memory system includes a memory array of cells arranged in "r" rows and "c" columns, with each row of cells connected to a write conductor and to a separate read conductor. The memory array may be simultaneously written into and read from by a write address decoder having "r" outputs, one output connected to and corresponding to each write conductor and a read address decoder having "r" outputs, one output connected to and corresponding to each read conductor. Control signals are applied to the write address decoder to cause the outputs of the write address decoder to scan the memory array at a first rate, in sequence, in a first direction, and control signals are applied to the read address decoder to cause the outputs of the read address decoder to scan the memory array at a second rate, in sequence, in a second direction, opposite the first direction. The first and second rates and the number of rows of the memory array are selected such that no memory location is written into and read from during the same time interval, preventing interference between the read and write functions.

Claims11

Dependent claims

A combination comprising:

a memory array of cells arranged in "r" rows and "c" columns each row of cells connected to a write row line for controlling the writing of information into the cells of the row and a read row line for controlling the reading of information stored in the cells of the row;
a write address decoder having "r" write address outputs, one write address output corresponding to each write row line of the memory array and being connected thereto;
a read address decoder having "r" read address outputs, one read address output corresponding to each read row line of the memory array and being connected thereto;
means coupled to the write address decoder and to the read address decoder for generating signals at the outputs of the write and read address decoders for energizing the outputs of the write address decoder and its corresponding write row lines in an ascending sequence from 1 to r, at a rate of Fs and for generating signals energizing the outputs of the read address decoder and its corresponding read row lines in a descending order from the rth row to the first row at a rate of nFs;
where n is an integer, and Fs is a selected frequency.

2 more elements

Dependencies are inferred from the claim text.

Random access memory with circuitry for concurrently and sequentially writing-in and reading-out data at different rates

Life of this patent

Random access memory with circuitry for concurrently and sequentially writing-in and reading-out data at different rates

Life of this patent

Abstract

Claims11