Flash memory having transistor redundancy
AssigneeMicron Technology, Inc.
InventorsRoger R. Lee, Fernando Gonzalez
Life of this patent
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Abstract
A flash programmable memory device comprises first and second row lines each having memory elements therealong with the second conductive line functionally replacing the first conductive line. The memory device further includes a first program circuit for programming the memory elements along the first row line, and a second program circuit for programming memory elements along the second row line. A read circuit bypasses the first conductive line during all read cycles and reads the memory elements along the second row line.
Claims20
A memory device responsive to first and second voltage signals comprising:
- a) at least one redundant row line having a plurality of transistors and a pass transistor;
- b) a plurality of primary row lines coupled with said first and second voltage signals, each primary row line having a plurality of memory transistors, each primary row line responsive to a redundancy signal and having associated therewith:
- i) a primary redundancy signal path for carrying said redundancy signal;
- ii) a pass transistor which electrically couples said redundancy signal path and said primary row line such that a third potential on said redundancy signal path deactivates said pass transistor and a fourth potential on said redundancy signal path activates said pass transistor,
- wherein said third potential on said redundancy signal path ties said row line to said first voltage signal and said fourth potential on said redundancy signal path ties said row line to said second voltage signal.
A programmable memory device responsive to first and second voltage signals and having a redundancy signal path, comprising:
- a) a first transistor having a source region coupled with said first voltage signal, a drain region, and a gate coupled with a timer output;
- b) a second transistor having a source region coupled with said first transistor drain region, a drain region, and a gate coupled with said redundancy signal path;
- c) a primary row line coupled with said second transistor drain region;
- wherein a first potential on said redundancy signal path and a second potential on said timer output couples said primary row line with said first voltage signal, and a third potential on one of said redundancy signal path and said timer output isolates said primary row line from said first voltage signal.
A flash memory device comprising:
- a) a plurality of primary row lines each having a plurality of memory transistors therealong;
- b) a plurality of primary column lines which intersect said primary row lines;
- c) a plurality of redundant row lines each having a plurality of memory transistors therealong;
- d) a unique redundancy signal path associated with each primary and redundant row line,
- wherein as a first potential is applied to one of said redundancy signal paths said row line associated with said one redundancy signal path is coupled to a first voltage signal, and as a second potential is applied to said one redundancy signal paths said row line associated therewith is coupled to a second voltage signal.
Dependencies are inferred from the claim text.