Synchronous memory packaged in single/dual in-line memory module and method of fabrication

A dual in-line memory (DIMM) module comprising:

• a printed circuit board having a first side, a second side, and a connector edge, said connector edge having a plurality of electrical contacts on said first side and said second side;
• a set of first memory elements arranged on the first side of said printed circuit board, at least some of said first memory elements having data lines and control lines coupled to selected electrical contacts of said plurality of electrical contacts on said connector edge of said printed circuit board;
• a set of second memory elements arranged on the second side of said printed circuit board, at least some of said second memory elements also having data lines and control lines coupled to selected electrical contacts of said plurality of electrical contacts on said connector edge of said printed circuit board;
• and
• a plurality of first capacitive means and a plurality of second capacitive means, each first capacitive means being associated with one of said at least some first memory elements and said at least some second memory elements having data lines and control lines coupled to said selected electrical contacts on said connector edge of said printed circuit board, and each second capacitive means also being associated with one of said at least some first memory elements and said at least some second memory elements having said data lines and said control lines coupled to said selected electrical contacts on said connector edge of said printed circuit board, wherein each of said at least some first memory elements and said at least some second memory elements has associated therewith both a first capacitive means and a second capacitive means, said associated first capacitive means being disposed and connected to function as a data line decoupling capacitor and said associated second capacitive means being disposed and connected to function as a control line decoupling capacitor.

A single in-line memory module (SIMM) comprising:

• a printed circuit board having a planar surface and a connector edge, said connector edge having a plurality of electrical contacts;
• a set of memory elements arranged on the planar surface of the printed circuit board, at least some of the memory elements having data lines and control lines coupled to selected electrical contacts of the plurality of electrical contacts on the connector edge of the printed circuit board;
• and
• a plurality of first capacitive means and a plurality of second capacitive means, each first capacitive means being associated with one of said at least some memory elements having data lines and control lines coupled to said selected electrical contacts on the connector edge of the printed circuit board, and each second capacitive means also being associated with one of the at least some memory elements having data lines and control lines coupled to the selected electrical contacts on the connector edge of the printed circuit board, wherein each of said at least some memory elements has associated therewith a first capacitive means of said plurality of first capacitive means and a second capacitive means of said plurality of second capacitive means, each associated first capacitive means being disposed and connected to function as a data line decoupling capacitor and each associated second capacitive means being disposed and connected to function as a control line decoupling capacitor.

A method for defining an "x" pin dual in-line memory module (DIMM) for synchronous dynamic random access memories (SDRAMs) from a standard "x" pin DIMM for dynamic random access memories (DRAMs) having column enable (CE) and row enable (RE) pins, said method comprising the steps of:

• (a) reassigning column enable (CE) pins and row enable (RE) pins of said "x" pin DIMM design for DRAMs to data input/output mask (DQMs) pins and chip select (CS) pins, respectively;
• (b) reassigning at least one pin of said "x" pin DIMM design for DRAMs to comprise a synchronous clock (CLK) pin;
• and
• (c) reassigning at least one pin of said "x" pin DIMM design for DRAMs to comprise a synchronous column address strobe (SCAS) pin and one pin of said "x" pin DIMM design for DRAMs to comprise a synchronous row address strobe (SRAS) pin,
• wherein upon completion of said steps (a)-(c) a functional "x" pin DIMM design for SDRAMs is defined from the standard "x" pin DIMM design for DRAMs.