US 5,513,132 A · Zero latency overhead self-timed iterative logic structure and method

Abstract

A novel third phase of CMOS domino logic is identified and used in the logic system of the present invention to store data. The use of this third phase in addition to the normally used precharge and logic evaluation phases, provides a logic structure of cascaded domino logic gates which are pipelined without intervening latches for memory storage. The memory storage function of the conventional latches being provided by the third logic phase. The novel approach requires that the functional inputs to this system have strictly monotonic transitions during the logic evaluation phase, and requires that the precharge signal must be active during only the precharge phase. Embodiments of the pipelined system according to the invention, are structured so that the output of the pipeline are fed back to the input of the pipeline to form an iterative structure. Such a feedback pipeline is viewed as a "loop" or "ring" of logic. The logic ring circulates data until the entire computation is complete. A method for using the logic structure is also described.

Claims52

Dependent claims

A method for use with an apparatus, said apparatus including a plurality of function blocks, said plurality of function blocks being arranged in preceding and trailing orders, said method comprising the steps of:

evaluating at least one functional input signal by a function block during an evaluation phase;
sustaining and providing evaluated input signal during a storage phase;
detecting completion of output signal generation by said function block;
and
resetting respective trailing function block in response to detection of said completion of output signal generation during a reset phase.

2 more elements

An apparatus for computing a logical or arithmetic result from input data, said apparatus comprising:

a plurality of function blocks for generating a functional output in response to at least one functional input, said functional input comprising at least one input signal;
each of said plurality of function blocks including a reset port for receiving a reset signal, an input port for receiving said at least one functional input, storage means for storing said functional output, and an output port for communicating said functional output;
said plurality of function blocks arranged in pair-wise-relative leading and trailing order, wherein said output port of one of said trailing function blocks is coupled directly to said input port of at least one of said leading function blocks, and wherein said input port of one of said leading function blocks is coupled directly to said output port of at least one of said trailing function blocks;
said plurality of function blocks being interconnected without interposing a separately controlled storage element between any of said function blocks;
and
control means coupled with each said pair-wise-relative trailing function blocks for generating said reset signal to select the operational phase of said trailing function blocks in response to characteristics of said functional output of at least one of said pair-wise-relative leading function blocks.

3 more elements

Dependencies are inferred from the claim text.

Zero latency overhead self-timed iterative logic structure and method

Life of this patent

Zero latency overhead self-timed iterative logic structure and method

Life of this patent

Abstract

Claims52