Logic placement using positionally asymmetrical partitioning method

A partitioning method for placing a circuit design into a programmable integrated circuit device having a distribution of physical resources along a horizontal line, the circuit design comprising a plurality of circuit elements, some of which are to be distributed to said physical resources along a horizontal line, the method comprising:

• identifying specific circuit elements of the plurality of circuit elements to be placed along a horizontal line;
• attaching constraints to lines connected to said circuit elements identified as elements to be placed along a horizontal line, said constraints identifying elements to be moved if the horizontal line is moved;
• and
• partitioning the plurality of circuit elements according to a min-cut procedure such that when a member of a marked group is moved across a horizontal cut line, other members of the group are also moved across the horizontal cut line.

A partitioning method for placing a circuit design into a programmable integrated circuit device having a plurality of types of physical resources distributed along horizontal or vertical lines, the circuit design comprising a plurality of circuit elements, the method comprising the following steps:

• identifying and assigning to single cells those elements of said plurality of circuit elements associated with one of said plurality of types of physical resources;
• partitioning said circuit design during a first phase until all of said single cells are in their own groups and all of said circuit elements which are not part of said single cells are in their own groups;
• decomposing said single cells into source circuit elements from which they were composed and marking said source circuit elements to indicate a type of said plurality of types of physical resources with which they are associated;
• adjusting X ranges and Y ranges of said source circuit elements to reflect alignments of said types of physical resources with which said source circuit elements are associated;
• and
• partitioning said circuit design during a second phase, wherein partitioning of said source circuit elements is restricted according to said alignments of said types of physical resources with which they are associated.