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US 5,513,123 AGranted
Non-scan design-for-testability of RT-level data paths
AssigneeNEC USA, Inc.
InventorsSujit Dey, Miodrag Potkonjak
Life of this patent
Estimating the term…
Abstract
Non-scan design-for-testability methods for making register-transfer-level data path circuits testable include using EXU S-graph representation of the circuits. Loops in the EXU S-graph are made k-level controllable/observable to render the circuit testable without having to scan any flip-flops or break loops directly. Moreover, the resultant circuit is testable at-speed.
Claims14
A method of non-scan design-for-testability of circuits comprising the steps of:
- defining a circuit to be synthesized functionally in terms of a register-transfer level data path;
- modifying the register-transfer level data path by adding observable points and controllable points to render the circuit to be k-level controllable and/or observable;
- and
- synthesizing the circuit including the modifications to enable the circuit to be tested at-speed.
1 more element
A method of non-scan design-for-testability of circuits comprising the steps of:
- defining a circuit to be synthesized functionally in terms of a register-transfer level data path;
- modifying the register-transfer level data path by adding constants for providing observable points and controllable points to render the circuit to be k-level controllable and/or observable;
- and
- synthesizing the circuit including the modifications to enable the circuit to be tested at-speed.
1 more element
Dependencies are inferred from the claim text.