Hierarchical floorplanner for gate array design layout

A method of placing a plurality of design elements on an integrated circuit using a placement system, said method comprising the steps of:

• supplying the placement system with input information to define said design elements and said integrated circuit,
• enabling a user to select positions of input/output terminals on said integrated circuit for connecting said design elements on said integrated circuit with external circuitry based on said input information,
• hierarchically grouping said design elements into a plurality of groups,
• prior to the placement of the design elements, determining the size of regions on said integrated circuit to be occupied by said groups using said input information, based on the number of basic cells in each of the groups and the area of one of the basic cells,
• enabling the user to place said groups on said integrated circuit based on the determined size of said regions and the selected positions of the input/output terminals.

In an element placement system having a display for visualizing layout of an integrated circuit comprising a plurality of logic cells, a method for grouping said logic cells comprising the steps of:

• supplying the placement system with input information to define said logic cells and said integrated circuit,
• combining said logic cells into a plurality of groups defined by the size of an area on said integrated circuit to be occupied by each group, the size of said area being determined prior to the placement of the logic cells, based on the size of said logic cells in the group and the number of the logic cells in the group,
• displaying said plurality of groups and said integrated circuit on said display,
• moving said plurality of groups to selected positions on said integrated circuit.

A placement system controlled by a user for hierarchically grouping a plurality of design elements into groups and selecting their positions on a design area, comprising:

• means responsive to input information for creating a database defining said design elements and said design area,
• means responsive to said database for enabling said user to select positions of input/output terminals on said design area for connecting said design elements within said design area with circuitry outside said design area,
• means responsive to said database for determining, prior to the placement of the design elements, the size of regions on said design area to be occupied by said groups of design elements, based on the number of basic cells in each of the groups and the area of one of the basic cells,
• means responsive to the determined size of said regions and the selected positions of the input/output terminals for indicating to said user places of said groups on said design area.