Sample rate converter

Apparatus for converting the sampling rate of a digital signal from f.sub.1 to f.sub.2 comprising:

• a) memory means for storing a plurality of adjacent samples of the digital signal;
• b) means for forming a second signal at a sampling frequency of f.sub.2, said means comprising:
• i) means for generating a ramp signal;
• ii) means for quantizing the ramp signal into one of a plurality of quantization levels, with each of the plurality of quantization levels corresponding to one of the plurality of adjacent samples stored in the memory means;
• and
• iii) means for selecting at a frequency of f.sub.2 the samples stored in the memory means corresponding to the quantized value of the ramp signal;
• and
• d) a low pass filter coupled to the means for forming a second signal.

Apparatus for converting the sampling rate of a digital signal from f.sub.1 to f.sub.2 comprising:

• a) at least two registers, each having an input, an output and clock input, interconnected to form a shift register chain, with the input of the first register in the shift register chain adapted to receive the digital signal;
• b) a multiplexer having a plurality of inputs, a control input and one output, each of the plurality of inputs coupled to one of the at least two registers and said output forming the output of the apparatus;
• c) a sigma-delta modulator having an input, an output coupled to the control input of the multiplexer and a clock input;
• d) a means for generating a clock signal at a frequency f.sub.2, said means coupled to the clock input of the sigma-delta modulator;
• e) a means for generating a clock signal at the frequency f.sub.1, said means connected to the clock input of each of the at least two registers;
• and
• f) means for generating a ramp signal increasing a rate proportional to f.sub.1, said means coupled to the input of the sigma delta modulator.

A mixed signal tester having circuitry to apply an analog signal to a device under test, said circuitry comprising:

• a) a memory storing samples of at least one period of at least one stimulus signal;
• b) control means, coupled to the memory, for retrieving samples from the memory at a selectable rate f.sub.1 ;
• c) means for converting the sampling rate of the signal retrieved from memory from f.sub.1 to f.sub.2 ;
• d) a digital to analog converter operating at a frequency f.sub.2 having a digital input and an analog output, said digital input coupled to the means for converting;
• e) format circuit means, coupled to the analog output of the digital to analog converter, for applying the signal at the analog output to a device under test.