Amplifier stage having compensation for NPN, PNP beta mismatch and improved slew rate

A method of compensating an amplifier for a systematic voltage offset, the amplifier having a stage having first and second output transistors, comprising the steps of:

• sourcing a first variable current to a first current handling terminal of the first output transistor;
• and
• sinking a second variable current from a first current handling terminal of the second output transistor;
• wherein the first current and second current are each variable to minimize the systematic voltage offset of the amplifier;
• and
• controlling the first current in response to a voltage at a current handling terminal of the first transistor.

An amplifier stage having improved slew rate performance, comprising:

• a signal input terminal;
• an input transistor having its control terminal connected to the signal input terminal and having first and second current handling terminals;
• an output transistor having its control terminal connected to the second current handling terminal of the input transistor and having first and second current handling terminals;
• and
• a current boost transistor having its control terminal connected to the signal input terminal and having first and second current handling terminals, the first current handling terminal being connected to the control terminal of the output transistor, and the second current handling terminal being connected to a constant current source.

A method of operating an amplifier stage having an output transistor controlled by an input signal which includes fast slewing portions, comprising the steps of:

• during times other than fast slewing portions of the signal, providing a particular level of current to the output transistor;
• during a fast slewing portion of the signal, providing an additional current to a control terminal of the output transistor, the additional current being generated in response to the fast slewing portion of the signal;
• and
• providing a current boost at a current handling terminal of the output transistor.

An amplifier stage compensated for systematic voltage offset, the stage having first and second transistors and comprising:

• a first controllable current source connected to a first current handling terminal of the first transistor;
• and
• a second controllable current source connected to a first current handling terminal of the second transistor;
• wherein a second current handling terminal of the first transistor is connected to a first circuit node of the amplifier, and a second current handling terminal of the second transistor is connected to a second circuit node of the amplifier stage, there being a beta mismatch between the first and second circuit nodes;
• and wherein the first and second controllable current sources provide respectfully first and second current levels, the first current level plus the current at the first circuit node being approximately equal to the second current level plus the current at the second circuit node;
• wherein the first controllable current source includes a constant current source connected to a first current handling terminal of a control transistor, a control terminal of the control transistor being connected to the first current handling terminal of the first transistor.