Bootstrap circuit

A bootstrap circuit adapted to a wordline enable circuit having a wordline driver for driving a wordline and a row decoder for decoding a row address signal to control the wordline driver, the bootstrap circuit comprising:

• a first inverter for inverting an output signal of the wordline driver;
• a capacitor being coupled between an output terminal of the wordline driver and a node;
• a second inverter being coupled between the output terminal of the wordline driver and said capacitor to invert the output signal of the wordline driver;
• a voltage transfer means for transferring a voltage signal from the row decoder to said node;
• an NMOS pull-up driver for transferring the output signal of the wordline driver inverted by said first inverter to the wordline, in response with a voltage signal from said node;
• a third inverter for inverting the voltage signal from the row decoder;
• and
• an NMOS pull-down driver for transferring a ground voltage to the wordline in response with the voltage signal of the row decoder inverted by said third inverter.

A bootstrap circuit adapted to a data output buffer having an NMOS pull-up driver, a power supply voltage from a power supply source to an outlet line in response with a data signal from an inlet line, an NMOS pull-down driver for transferring a ground voltage to the outlet line and a pull-down controller being connected between the inlet line and the NMOS pull-down driver for complementally driving the NMOS pull-down driver for the NMOS pull-up driver in response with the data signal from the inlet line, the bootstrap circuit comprising:

• a first inverter being coupled between the inlet line and the NMOS pull-up driver for inverting the data signal from the inlet line;
• a second inverter for inverting the data signal from the inlet line;
• a first capacitor being coupled between an output terminal of said second inverter and a node;
• a delay means for delaying the data signal from the inlet line for a predetermined time period;
• a signal transfer means for the data signal delayed by said delay means to said node;
• and
• an NMOS transistor being coupled between an output terminal of said first inverter, the NMOS pull-up driver and said node for transferring the data signal inverted by said first inverter to the NMOS pull-up driver in response with a voltage signal on said node.