Current mirror circuit with current-compensated, high impedance output

A current mirror circuit for conducting a reference current and in accordance therewith conducting an output current proportional thereto, comprising:

• a first transistor which includes a first emitter, a first base and a first collector, wherein said first emitter is coupled to a shared node and said first collector is coupled to a reference node for conducting a reference current;
• a second transistor which includes a second emitter, a second base and a second collector, wherein said second emitter is coupled to said shared node and said second base is coupled to said first transistor base;
• and
• a third transistor which includes third and fourth emitters, a third base and a third collector, wherein said third emitter is coupled to said second transistor collector, said fourth emitter is coupled to said second transistor base, said third base is coupled to said reference node and said third collector is for conducting an output current which is selectively proportional to said reference current.

A current mirror circuit for conducting a reference current and in accordance therewith conducting a plurality of load currents, comprising:

• an input transistor which includes an input emitter, an input base and an input collector, wherein said input emitter is coupled to a shared node and said input collector is coupled to a reference node for conducting a reference current;
• and
• a first output device group for conducting a first load current which is selectively proportional to said reference current, wherein said first output device group includes:
• a first output transistor which includes a first output emitter, a first output base and a first output collector, wherein said first output emitter is coupled to said shared node and said first output base is coupled to said input transistor base;
• a second output transistor which includes a second output emitter, a second output base and a second output collector, wherein said second output emitter is coupled to said first output transistor collector, said second output base is coupled to said reference node and said second output collector is for conducting an output current;
• and
• a third output transistor which includes a third output emitter, a third output base and a third output collector, wherein said third output emitter is coupled to said first output transistor base, said third output base is coupled to said reference node and said third output collector is for conducting a compensation current;
• wherein a sum of said compensation current and said output current provides said first load current;
• and
• a second output device group for conducting a second load current which is approximately proportional to said reference current, wherein said second output device group includes:
• a fourth output transistor which includes a fourth output emitter, a fourth output base and a fourth output collector, wherein said fourth output emitter is coupled to said shared node and said fourth output base is coupled to said input transistor base;
• and
• a fifth output transistor which includes a fifth output emitter, a fifth output base and a fifth output collector, wherein said fifth output emitter is coupled to said fourth output transistor collector, said fifth output base is coupled to said reference node and said fifth output collector is for conducting said second load current.

A current mirror circuit for conducting a reference current and in accordance therewith conducting a plurality of load currents, comprising:

• an input transistor which includes an input emitter, an input base and an input collector, wherein said input emitter is coupled to a shared node and said input collector is coupled to a reference node for conducting a reference current;
• and
• a first output device group for conducting a first load current which is selectively proportional to said reference current, wherein said first output device group includes:
• a first output transistor which includes a first output emitter, a first output base and a first output collector, wherein said first output emitter is coupled to said shared node and said first output base is coupled to said input transistor base;
• and
• a second output transistor which includes second and third output emitters, a second output base and a second output collector, wherein said second output emitter is coupled to said first output transistor collector, said third output emitter is coupled to said first output transistor base, said second output base is coupled to said reference node and said second output collector is for conducting an output current;
• wherein said output current provides said first load current;
• and
• a second output device group for conducting a second load current which is approximately proportional to said reference current, wherein said second output device group includes:
• a third output transistor which includes a fourth output emitter, a third output base and a third output collector, wherein said fourth output emitter is coupled to said shared node and said third output base is coupled to said input transistor base;
• and
• a fourth output transistor which includes a fifth output emitter, a fourth output base and a fourth output collector, wherein said fifth output emitter is coupled to said third output transistor collector, said fourth output base is coupled to said reference node and said fourth output collector is for conducting said second load current.