MOS type semiconductor device having a low concentration impurity diffusion region

A complementary MOS type semiconductor device comprising a semiconductor substrate including an n-type region doped with n-type impurities and a p-type region doped with p-type impurities and having a surface, an n-channel MOS transistor formed in said p-type region, and a p-channel MOS transistor formed in said n-type region, said n-channel MOS transistor including:

• an n-type source region formed in said p-type region;
• an n-type drain region formed in said p-type region and separated from said n-type source region by a first predetermined distance;
• a first channel region formed in said p-type region and located between said n-type source region and said n-type drain region;
• a pair of n-type impurity diffusion regions formed on both sides of said first channel region and having an impurity concentration lower than that of said n-type source region;
• a first gate insulating film formed on said surface of said semiconductor substrate, said first gate insulating film directly covering said first channel region and said pair of n-type impurity diffusion regions, portions of said first gate insulating film above said pair of n-type impurity diffusion regions being thicker than a portion thereof above said first channel region;
• and
• a first gate electrode formed on said first gate insulating film,
• said p-channel MOS transistor including:
• a p-type source region formed in said n-type region;
• a p-type drain region formed in said n-type region and separated from said p-type source region by a second predetermined distance;
• a second channel region formed in said n-type region and located between said p-type source region and said p-type drain region;
• a second gate insulating film formed on said surface of said semiconductor substrate and having a uniform thickness;
• and
• a second gate electrode formed on said second gate insulating film.