Self-aligned gate sidewall spacer in a corrugated FET and method of making same
AssigneeInternational Business Machines Corporation
InventorAndres Bryant
Life of this patent
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Abstract
A self-aligned gate sidewall spacer and method of forming the sidewall spacer in a corrugated FET structure, comprising the steps of depositing a first oxide layer on a substrate; forming a substrate trench, having a substrate trench bottom and substrate trench sidewalls in the substrate; forming a gate electrode trench intersecting the substrate trench and filling the gate electrode trench with gate polysilicon for forming a gate electrode, the gate electrode having first and second gate sidewalls; depositing a second oxide layer over the gate electrode trench and substrate trench; and etching the second oxide layer for forming a sidewall spacer on each of the first and second gate sidewalls.
Claims13
A method of forming a self-aligned gate sidewall spacer in a corrugated field effect transistor (FET) structure, comprising the steps of:
- depositing a first oxide layer on a substrate;
- forming a substrate trench in the substrate, thereby defining a substrate trench bottom and substrate trench sidewalls;
- forming a gate electrode trench intersecting the substrate trench and filling the gate electrode trench with gate polysilicon for forming a gate electrode, said gate electrode defining first and second gate sidewalls;
- depositing a second oxide layer over the gate electrode trench and said substrate trench;
- and
- etching the second oxide layer for forming a sidewall spacer on each of said first and second gate sidewalls.
A method of forming a self-aligned gate sidewall spacer in a corrugated field effect transistor (FET) structure, comprising the steps of:
- depositing a first oxide layer on a substrate;
- etching a substrate trench in the first oxide layer and the substrate, thereby defining a substrate trench bottom and substrate trench sidewalls;
- forming nitride spacers on the substrate trench sidewalls;
- growing a thermal oxide pad layer on the substrate trench bottom;
- removing the nitride spacers and depositing a first layer of tetraethylorthosilicate (TEOS) on the substrate trench sidewalls;
- overfilling the substrate trench with intrinsic polysilicon;
- depositing a nitride layer;
- etching a gate electrode image in the nitride layer and intrinsic polysilicon for forming a gate electrode trench;
- growing a gate oxide on walls of the gate electrode trench;
- overfilling the gate electrode trench with gate polysilicon for forming a gate electrode having first and second gate sidewalls;
- recessing the gate polysilicon to a level below that of the nitride layer;
- filling the recess with a second layer of TEOS;
- removing the nitride layer;
- depositing a second oxide layer;
- etching the second oxide layer;
- etching the intrinsic polysilicon, stopping at the thermal oxide pad, thereby forming intrinsic polysilicon spacers on each of said first and second gate sidewalls;
- forming source and drain regions in the substrate trench sidewalls;
- removing the intrinsic polysilicon spacers selectively to oxide;
- overfilling the substrate and said gate electrode trenches with phosphosilicate glass (PSG) and planarizing the PSG to a level above the second layer of TEOS;
- and
- etching contact holes to expose the source and drain regions.
Dependencies are inferred from the claim text.