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US 5,512,502 AGranted
Manufacturing method for semiconductor integrated circuit device
AssigneeHitachi, Ltd.
InventorsFumio Ootsuka, Yusuke Nonaka, Atsumi Aoki
Life of this patent
Estimating the term…
Abstract
In forming a MISFET having a salicide structure, a polysilicon film forming a gate electrode in the MISFET is constructed of a first silicon film having a high n-type impurity concentration on the side of a gate insulating film and a second silicon film having a low n-type impurity concentration on the surface side of the gate electrode. Further, a Ti film is deposited on the second silicon film. The Ti film and the second silicon film are annealed twice at proper different temperatures to thereby promote a silicide reaction and form a low-resistance silicide layer in the second silicon film.
Claims24
A method of manufacturing a semiconductor device, comprising the steps of:
- (a) providing a semiconductor substrate with both a first silicon layer formed over a main surface of said substrate and a second silicon layer formed on said first silicon layer, said first silicon layer having an impurity concentration of n-type conductivity higher than that of said second silicon layer;
- (b) patterning said first silicon layer and said second silicon layer to form a gate electrode pattern in a MISFET;
- (c) depositing a first insulating film over said main surface after said step (b);
- (d) etching said first insulating film to form a side wall spacer on a side wall of said gate electrode pattern;
- (e) depositing a high-melting point metal film over said main surface, said gate electrode pattern, and said side wall spacer after said step (d);
- (f) performing first annealing to cause a silicide reaction between said second silicon layer having a shape of said gate electrode pattern and said high-melting point metal film and thereby form a first silicide layer in said second silicon layer;
- (g) removing an unreacted portion of said high-melting point metal film left on said main surface and said side wall spacer after said step (f);
- and
- (h) performing second annealing at a temperature higher than that of said first annealing after said step (g) to convert said first silicide layer into a second silicide layer having a resistance lower than that of said first silicide layer, said first silicon layer having an impurity concentration of 2.times.10.sup.20 atoms/cm.sup.3 or more, said second silicon layer having an impurity concentration of 1.times.10.sup.20 atoms/cm.sup.3 or less, an impurity concentration in an interface between said second silicide layer and said second silicon layer being 1.times.10.sup.20 atoms/cm.sup.3 or less.
6 more elements
A method of manufacturing a semiconductor device, comprising the steps of:
- (a) providing a semiconductor substrate with both a first silicon layer formed over a main surface of said substrate and a second silicon layer formed on said first silicon layer, said first silicon layer having an impurity concentration higher than that of said second silicon layer;
- (b) patterning said first silicon layer and said second silicon layer to form a gate electrode pattern in a MISFET;
- (c) depositing a first insulating film over said main surface after said step (b);
- (d) etching said first insulating film to form a side wall spacer on a side wall of said gate electrode pattern;
- (e) depositing a high-melting point metal (A) film over said main surface, said gate electrode pattern, and said side wall spacer after said step (d);
- (f) performing first annealing to cause a silicide reaction between said second silicon layer having a shape of said gate electrode pattern and said high-melting point metal film and thereby form a first silicide layer (ASi.sub.x ;
- x<2) in said second silicon layer;
- (g) removing an unreacted portion of said high-melting point metal film left on said main surface and said side wall spacer after said step (f);
- and
- (h) performing second annealing at a temperature higher than that of said first annealing after said step (g) to convert said first silicide layer into a second silicide layer (ASi.sub.2) having a resistance lower than that of said first silicide layer, an impurity concentration in an interface between said second silicide layer and said second silicon layer being 1.times.10.sup.20 atoms/cm.sup.3 or less.
7 more elements
A method of manufacturing a semiconductor device, comprising the steps of:
- (a) providing a first semiconductor substrate with both a first silicon layer formed over a main surface of said substrate and a second silicon layer formed over said first silicon layer, said second silicon layer having an impurity concentration lower than that of said first silicon layer, a gate electrode pattern of a MISFET being constituted by said first and second silicon layers;
- (b) forming side wall spacers on side surfaces of said first and second silicon layers, said side wall spacers being made of an insulating material;
- (c) forming a high-melting point metal film over said main surface, said second silicon layer and said side wall spacers;
- (d) performing a first annealing to cause a silicide reaction between said second silicon layer and said high-melting point metal film and thereby form a first silicide layer within said second silicon layer such that said first silicide layer does not reach said first silicon layer, said second silicon layer having an impurity concentration of 1.times.10.sup.20 atoms/cm.sup.3 or less;
- (e) removing an unreacted portion of said high-melting point metal film left on said main surface and said side wall spacers after step (d);
- and
- (f) performing a second annealing at a temperature higher than that of said first annealing after said step (e) to convert said first silicide layer to a second silicide layer having a resistance lower than that of said first silicide layer.
4 more elements
A method of manufacturing a semiconductor device, comprising the steps of:
- (a) providing a first semiconductor substrate with both a first silicon layer formed over a main surface of said substrate and a second silicon layer formed over said first silicon layer, said second silicon layer having an impurity concentration lower than that of said first silicon layer, a gate electrode pattern of an MISFET being constituted by said first and second silicon layers;
- (b) forming a high-melting point metal film over said main surface and said second silicon layer;
- (c) performing a first annealing to cause a silicide reaction between said second silicon layer and said high-melting point metal film and thereby form a first silicide layer within said second silicon layer such that said first silicide layer does not reach said first silicon layer, said second silicon layer having an impurity concentration of 1.times.10.sup.20 atoms/cm.sup.3 or less;
- (d) removing an unreacted portion of said high-melting point metal film left on said main surface after step (c);
- and
- (e) performing a second annealing at a temperature higher than that of said first annealing after said step (d) to convert said first silicide layer to a second silicide layer having a resistance lower than that of said first silicide layer.
3 more elements
Dependencies are inferred from the claim text.