US 5,512,397 A · Stepper scanner discretionary lithography and common mask discretionary lithography for integrated circuits

Abstract

Large scale integrated circuits are fabricated using redundant circuit elements to replace defective circuit elements by discretionary interconnect changes as determined by fine-grain testing of the integrated circuits after the logic units (such as individual transistors or logic gates) are fabricated and before they are electrically interconnected. The redundant circuit elements are then interconnected to non-defective circuit elements by one of two methods. In the first method a stepper-scanner apparatus modified to expose most of a resist layer defines the interconnect circuitry, but is shuttered-off over the discretionary interconnect changes. Then the discretionary interconnect changes are exposed by a conventional direct write on wafer pattern generation apparatus. In the second method, the interconnect patterning is accomplished by first fabricating a fixed custom mask defining the interconnect layer for a particular lot size (such as 100) of wafers. The fixed mask is fabricated after each wafer of the lot has been tested, and incorporates all the discretionary changes required to avoid interconnection to each defective circuit element in each of the wafers. The fixed custom mask is then used to expose the resist layer defining the interconnect circuitry for each of the 100 wafers.

Claims22

Dependent claims

A method of fabricating integrated circuits comprising the steps of:

fabricating a plurality of integrated circuit logic elements on a principal surface of a substrate;
forming a resist layer overlying the integrated circuit logic elements:
testing each logic element and determining the presence of defects in each logic element;
determining the location and dimensions of each defect;
providing a fixed mask;
exposing said resist layer with a first exposure through said fixed mask to define electrical interconnects between the logic elements on said resist layer and leaving predetermined portions of said resist layer unexposed, wherein said predetermined portions left unexposed are defined by the location and dimensions of each defect;
exposing said resist layer with a second exposure to define electrical interconnects between the logic elements on said resist layer by exposing only the predetermined portions left unexposed in the preceding step;
and
interconnecting the logic elements according to the first and second exposures, thereby excluding the logic elements having defects from the interconnected logic elements.

6 more elements

Dependencies are inferred from the claim text.

Stepper scanner discretionary lithography and common mask discretionary lithography for integrated circuits

Life of this patent

Stepper scanner discretionary lithography and common mask discretionary lithography for integrated circuits

Life of this patent

Abstract

Claims22