Data processing system having a switching network connecting multiple peripheral devices using data paths capable of different data bus widths

A data processing apparatus comprising:

• a first (k.times.m)-bit data bus for transmitting data of (k.times.m)-bits in parallel wherein k and m are an integer larger than one
• at least one (k.times.m)-bit I/O peripheral device connected to said first (k.times.m)-bit data bus;
• a first m-bit data bus group consisting of first to k-th m-bit data buses obtained by dividing said first (k.times.m)-bit data bus into k data buses having an equal width of data bus;
• a plurality of m-bit I/O data bus belonging to said first m-bit data bus group;
• a second (k.times.m)-bit data bus;
• a (k.times.m)-bit I/O central processing unit connected to said second (k.times.m)-bit data bus;
• a data path switching means connected between said first and second m-bit data bus groups which comprises a first group of m-bit bus transceivers each connecting one m-bit data bus belonging to said first group and a corresponding m-bit data bus belonging to said second group and a second group m-bit bus transceivers each connecting two m-bit data buses belonging to said second group;
• and
• a transmission control means for generating control signals responsive to a data transmission demand from said CPU and for selectively controlling said m-bit bus transceivers belonging to said first and second transceiver groups and said m-bit I/O peripheral devices corresponding to the control signals, thereby forming at least one data transmission path between two arbitrary devices selected from among said m-bit I/O peripheral devices, at least one (k.times.m)-bit I/O peripheral device and said CPU.