System for generating snoop addresses and conditionally generating source addresses whenever there is no snoop hit, the source addresses lagging behind the corresponding snoop addresses

In a multiprocessor system having a first and a second processor, a first and a second corresponding private cache, a shared memory, and an input/output (I/O) device, wherein cache coherency is maintained on a basis of a predetermined size (S), and I/O data stored in said shared memory are cacheable in said private caches, an apparatus for transferring I/O data between said shared memory and said I/O device and maintaining cache coherency, said apparatus comprising:

• a) address generation and control circuitry coupled to said I/O device for receiving from said I/O device a first write parameter denoting a starting memory location of a plurality of contiguous memory locations of said shared memory against which a plurality of write I/O data having a write I/O size (W) in integer multiple(s) of S from said I/O device are to be transferred to, in one or more transfers with each transfer transferring one cache coherency basis (CCB) of write I/O data,
• said address generation and control circuitry being also coupled to said shared memory and said private caches, and used for generating a plurality of write snoop addresses using said received first write parameter and S, outputting for said private caches said generated write snoop addresses to snoop said private caches, one write snoop address at a time,
• said address generation and control circuitry being also used for generating a plurality of write destination addresses using said output write snoop addresses, and outputting for said shared memory said generated write destination addresses to access said shared memory, one write snoop and destination address pair at a time with the write destination address lagging behind the corresponding write snoop address in a predetermined manner;
• b) a buffer coupled to said I/O device, said shared memory and said address generation and control circuitry for receiving from said I/O device said write I/O data, storing said received write I/O data, and outputting for said shared memory said stored write I/O data, one CCB of said write I/O data at a time and synchronous to said generating and outputting of write destination addresses.

In a multiprocessor system having a first and a second processor, a first and a second corresponding private cache, a shared memory, and an input/output (I/O) device, wherein cache coherency is maintained on a basis of a predetermined size (S), and I/O data stored in said shared memory are cacheable in said private caches, a method for transferring I/O data between said shared memory and said I/O device and maintaining cache coherency, said method comprising the steps of:

• a) receiving from said I/O device a first read parameter denoting a starting memory location of a plurality of contiguous memory locations of said shared memory from which a plurality of read I/O data having a read I/O size (R) in integer multiple(s) of S are to be transferred to said I/O device in one or more transfers with each transfer transferring one cache coherency basis (CCB) of read I/O data;
• b) generating a plurality of read snoop addresses using said received first read parameter and S, outputting for said private caches said generated read snoop addresses to snoop said private caches, one read snoop address at a time;
• c) concurrently but conditionally generating a plurality of read source addresses using said output read snoop addresses whenever said output read snoop addresses do not result in read snoop hit, and outputting for said shared memory said conditionally generated read source addresses to access said shared memory, one read source address at a time with the read source addresses lagging behind the corresponding read snoop addresses in a predetermined manner;
• and
• d) receiving from said share memory non-cached ones of said read I/O data, storing said received non-cached ones of said read I/O data, and outputting for said I/O device said stored non-cached ones of said read I/O data, one CCB of non-cached read I/O data at a time and synchronized to said generating and outputting of read source addresses.

In a multiprocessor system having a first and a second processor, a first and a second corresponding private cache, a shared memory, and an input/output (I/O) device, wherein cache coherency is maintained on a basis of a predetermined size (S), and I/O data stored in said shared memory are cacheable in said private caches, a method for transferring I/O data between said shared memory and said I/O device and maintaining cache coherency, said method comprising the steps of:

• a) receiving from said I/O device a first write parameter denoting a starting memory location of a plurality of contiguous memory locations of said shared memory against which a plurality of write I/O data having a write I/O size (W) in integer multiple(s) of S from said I/O device are to be transferred to, in one or more transfers with each transfer transferring one cache coherency basis (CCB) of write I/O data;
• (b) generating a plurality of write snoop addresses using said received first write parameter and S, outputting for said private caches said generated write snoop addresses to snoop said private caches, one write snoop address at a time;
• (c) generating a plurality of write destination addresses using said output write snoop addresses, and outputting for said shared memory said generated write destination addresses to access said shared memory, one write snoop and destination address pair at a time with the write destination address lagging behind the corresponding write snoop address in a predetermined manner;
• and
• (d) receiving from said I/O device said write I/O data, storing said received write I/O data, and outputting for said shared memory said stored write I/O data, one CCB of said write I/O data at a time and synchronous to said generating and outputting of write destination addresses.