Configurable network using dual system busses with common protocol compatible for store-through and non-store-through cache memories

In a network utilizing a dual system bus means connected to main memory and using a common protocol compatible for data transfers between processor modules with Store-Through cache memory units and processor modules with Non-Store-Through cache memory units which intercommunicate with a plurality of interbus processor interface modules using Non-Store-Through cache memory units, a system for data transfers between said processor modules and interbus processor interface modules, each of which can operate independently as a sending module and a receiving module, said system comprising:

• (a) means to configure said network so that a first bus is dedicated to processor modules having Store-Through (ST) cache memory units and the second bus is dedicated to said processor modules having Non-Store-Through cache memory units;
• (b) means to configure said network so that both first and second busses are dedicated to said processor modules having Non-Store-Through (NST) cache memory units;
• (c) a plurality of digital modules connected to said dual system bus means using a common data transfer protocol for each digital module, said digital modules including:
• (c1) first and second processor modules each having a Non-Store-Through (NST) cache memory unit;
• (c2) first and second interbus-processor message interface unit modules;
• (c3) main memory module means;
• (d) said dual bus means including first and second busses each of which includes:
• (d1) an address/command/data line;
• (d2) a control line for enabling/disabling said digital modules;
• (d3) a status line for conveying information on the status of each digital module;
• (d4) an arbitration line to grant/deny bus access to a requesting module;
• (d5) a common clock line for synchronous clock signals;
• (e) common data transfer protocol means for regulating data transfers between sending and receiving digital modules;
• (f) spy logic means in each of said first and second processor modules and said interbus processor message interface unit modules for detecting data writes occurring in any of said processor modules NST cache memory units and in any of said interbus-processor message interface unit modules;
• (g) means to invalidate in each module, any existing copies of data having an address that had been overwritten.

In a network utilizing a dual system bus means with first and second busses which are connected to main memory and which use a common protocol compatible for data transfers between processor modules with Store-Through cache memory units and processor modules with Non-Store-Through cache memory units which intercommunicate with a plurality of interbus processor interface modules using Non-Store-Through cache memory units, a method for data transfers between said processor modules and interbus processor interface modules, each of which can operate independently as a sending module and a receiving module, comprising the steps of:

• (a) requesting bus access by a sending module, to any one of said dual system bus means;
• (b) arbitrating when said sending module will be given access to one bus of said dual system bus means based on a rotating priority access algorithm which insures fairness of access to each module;
• (c) transmitting, by said sending module, when bus access is granted, a command, destination address, and data words to a target receiver module;
• (d) checking said bus to sense if a Not Ready signal or Bus Error signal appears;
• (e) replying, by said target receiver module, with an acknowledgment to said sending module, if no Not Ready or Bus Error signal appears;
• (f) placing, by said sending module, of a Busy signal on said bus to prevent bus access by any other modules seeking bus access;
• (g) returning, by said receiver module, to said sending module, data words requested by said sending module;
• (h) releasing said bus, by said sending module, for use by another sending module;
• (i) configuring said network so that said first bus in said dual system bus means is dedicated to processor modules having Store Through cache memory units and said second bus is dedicated to processor modules using Non-Store-Through cache memory units;
• (j) configuring said network so that said first and second busses of said dual system bus means are dedicated only for use of processor modules having Non-Store-Through cache memory units.