Priority encoder

A priority encoder, which detects an active bit (first level) located nearest to a most significant bit (MSB) or nearest to a least significant bit (LSB) among 2.sup.n bits of input data and converts the input data into n bits of coded output data, said priority encoder comprising:

• a set of selectors, the set having 2.sup.n selectors interconnected in order from the MSB to the LSB of input data, each selector including
• at least one switch circuit responsive to a respective bit of input data, having respective terminals A and B, and having a switching element connected between the respective terminals A and B;
• the set of 2.sup.n selectors having
• carry line means for connecting the respective terminal A of the included at least one switch circuit of a particular selector into a respective neighboring one of the selectors for a next more significant bit in sequential order to the respective terminal B of the respective at least one switch circuit included in the respective neighboring one selector, for connecting the respective terminal B of the included at least one switch circuit into another respective neighboring selector for a next less significant bit in sequential order to the respective terminal A of the respective at least one switch circuit included in the respective other neighboring selector to provide series connection of the switching elements in at least a subset of the set of 2.sup.n selectors;
• the priority encoder further comprising:
• an encoder connected to said set of 2.sup.n selectors, receiving outputs from said set of 2.sup.n selectors, and sending a signal of n bits of coded output data transformed from the outputs from said set of 2.sup.n selectors;
• means for closing each switching element in response to the respective bit of input data received as an inactive bit (second level) and for opening each switching element in response to the respective bit of input data received as an active bit and for detecting among the open switching elements a particular open switching element distinguished by location with respect to the MSB or the LSB;
• a first discharge circuit connected between ground potential and terminal A of said switch circuit receiving the MSB of input data and a second discharge circuit connected between ground potential and terminal B of said switch circuit receiving the LSB of input data;
• means for controlling the discharge circuits in response to a detection of an open circuit nearest to the MSB or the LSB;
• and a precharge circuit including at least one p-channel MOS transistor connected between a power supply terminal and the carry line of each respective particular selector, the switching element included in the respective particular selector including an n-channel MOS transistor having a gate for receiving an input data bit and having a source and a drain connected in series with the carry line, the discharge circuits including n-channel transistors connected between ground potential and the respective one of said terminal A of the switch circuit receiving the MSB input data and said terminal B of the switch circuit receiving the LSB of input data.

A priority encoder, which detects an active bit located nearest to a most significant bit (MSB) or nearest to a least significant bit (LSB) among 2n bits of input data and converts the input data into n bits of coded output data, said priority encoder comprising:

• a first discharge circuit, controlled by a first discharge signal, for outputting a first potential;
• a second discharge circuit, controlled by a second discharge signal, for outputting the first potential;
• 2n switch circuits connected in series between the first and second discharge circuits, each of the switch circuits being controlled by a predetermined bit among 2n bits of the input data;
• a plurality of precharge circuits for outputting a second potential, the precharge circuits being controlled by a precharge signal, and each connected to connection points between switch circuits, between the first discharge circuit and the 2n switch circuits, and between the second discharge circuit and the 2n switch circuits;
• 2n detectors each respectively connected to a respective pair of different points in the 2n switch circuits to detect and output an active bit when the two different points have different potentials;
• an encoder stage for converting 2n bits of the data output from 2n of the detectors to n bits of coded data.