Multi-clock SIMD computer and instruction-cache-enhancement thereof

A multi-clock SIMD computer comprising:

• a globel instruction broadcast subsystem regulated by a system clock signal oscillating at a system clock rate;
• an MCS regulated by a second clock signal;
• and
• a PE module coupled to said global instruction broadcast subsystem and to said MCS, said PE module implemented on a single chip and including:
• a first internal subsystem regulated by a third clock signal;
• a second internal subsystem regulated by a fourth clock signal;
• and
• a multi-clock generating circuit, responsive to said system clock signal, for generating a plurality of clock signals including said second, third, and fourth clock signals, wherein one of said third and fourth clock signals is a PE module clock signal oscillating at a PE module clock rate higher than said system clock, wherein said second internal subsystem includes a processing element (PE) that is regulated by a PE clock signal, and wherein said plurality of clock signals includes said PE clock signal oscillating at a PE clock rate higher than said system clock rate but no higher than said PE module clock rate.

A multi-clock SIMD computer comprising:

• a global instruction broadcast subsystem regulated by a system clock signal oscillating at a system clock rate;
• an MCS regulated by a second clock signal;
• and
• a PE module coupled to said global instruction broadcast subsystem and to said MCS, said PE module implemented on a single chip and including:
• a first internal subsystem regulated by a third clock signal;
• a second internal subsystem regulated by a fourth clock signal;
• and
• a multi-clock generating circuit, responsive to said system clock signal, for generating a plurality of clock signals including said second, third, and fourth clock signals, wherein said first clock signal oscillates at a rate different from one of said second, third, and fourth clock signals, and wherein said plurality of clock signals includes one clock signal oscillating in-phase with said system clock signal.

A multi-clock SIMD computer comprising:

• a global instruction, broadcast subsystem regulated by a system clock signal oscillating at a system clock rate;
• an MCS regulated by a second clock signal;
• and
• a PE module coupled to said global instruction broadcast subsystem and to said MCS, said PE module implemented on a single chip and including:
• a first internal subsystem regulated by a third clock signal;
• a second internal subsystem regulated by a fourth clock signal:
• and
• a multi-clock generating circuit, responsive to said system clock signal, for generating a plurality of clock signals including said second, third, and fourth clock signals. Wherein one of said third and fourth clock signals is a PE module clock signal oscillating at a PE module clock rate higher than said system clock, and wherein a first one of said plurality of clock signals may be restarted during any cycle of said PE module clock signal.

A multi-clock SlMD computer comprising:

• a global instructing broadcast subsystem regulated by a system clock signal oscillating at a system clock rate;
• an MCS regulated by a second clock signal;
• and
• a PE module coupled to said global instruction broadcast subsystem and to said MCS, said PE module implemented on a single chip and including:
• a first internal subsystem regulated by a third clock signal;
• a second internal subsystem regulated by a fourth clock signal;
• and
• a multi-clock generating circuit, responsive to said system clock signal, for generating a plurality of clock signals including said second, third, and fourth clock signals, wherein one of said third and fourth clock signals is a PE module clock signal oscillating at a PE module clock rate higher than said system clock;
• wherein said global instruction broadcast subsystem includes:
• a system controller for providing a first sequence of instructions to said PE module;
• and
• a global instruction broadcast network, coupled to said system controller, for broadcasting said first sequence of instructions from said system controller to said PE module at said system clock rate;
• and
• wherein said first internal subsystem is regulated by said PE module clock signal and includes a sub-broadcast-interval instruction sequencer, coupled to said global instruction broadcast network, for supplying said first sequence of instructions to said second internal subsystem at said PE module clock rate.

A processing element (PE) module for use in a multi-clock, single-instruction stream, multiple-data stream (SIMD) computer having a system controller, a global instruction broadcast network, and an inter-PE communication network (ICN), and being regulated by a system clock signal oscillating at a system clock rate, said PE module comprising:

• a plurality of processing elements all regulated by a PE module clock signal;
• a multi-chip subsystem (MCS) access controller, coupled to said plurality of processing elements, for selectively coupling said plurality of processing elements to said ICN, wherein said MCS access controller is regulated by said PE module clock signal;
• a local controller coupled to said global instruction broadcast network, said local controller including:
• an instruction decoder circuit, responsive to an instruction from said global instruction broadcast network, for generating a decoded instruction and an ICN control signal, wherein said instruction decoder circuit is regulated by said PE module clock signal;
• an ICN control re-timer circuit, coupled to said instruction decoder circuit, for receiving said ICN control signal from said instruction decoder circuit and retransmitting Said ICN control signal to said MCS access controller, wherein said ICN control signal re-timer circuit is regulated by an ICN clock signal;
• and
• a multi-clock generator circuit, responsive to said system clock signal, for generating a plurality of clock signals, wherein said plurality of clock signals includes said PE module clock signal oscillating at a PE module clock rate and said ICN clock signal oscillating at a ICN clock rate, wherein said PE module clock rate and said ICN clock rate are no lower than said system clock rate;
• and
• a local instruction broadcast network, coupled to said local controller, said plurality of processing elements, and said MCS access controller, for transferring said decoded instruction from said local controller to said plurality of processing elements and said ICN control signal from said local controller to said MCS access controller.