Vector processing device using address data and mask information to generate signal that indicates which addresses are to be accessed from the main memory

A vector processing device comprising:

• a vector processing portion having at least one vector register, and a vector control register to store mask information indicating valid bits of vector data which are to be processed by said vector processing device;
• a storage;
• and
• a storage controller to control access to said storage, said storage controller having
• address data selection means for generating a selected address signal which indicates selected locations in said storage which are to be accessed, said address data selection means including
• access information registration means having an address information registration means for storing address data corresponding to locations in said storage which are to be accessed,
• mask registration means for keeping the mask information received from said vector control register, and
• access control means which selects addresses among said address data which correspond to said valid bits of said mask information to generate said selected address signal, and
• data storage means for storing load data obtained from said storage using said selected address signal to said at least one vector register, said data storage means further including
• load data storage means for temporarily storing said load data, and
• load data expansion means which expands said load data temporarily held in accordance with said mask information and stores them in said at least one vector register.