Performing system tasks at power-off using system management interrupt

A computer system comprising:

• (a) a CPU capable of executing application program code and BIOS code and having a system management interrupt characterized by being a non-maskable interrupt, the interrupt handler of which cannot be altered by application program code;
• (b) a power management processor in circuit communication with said CPU via said system management interrupt and operative to activate said CPU's system management interrupt;
• (c) a power supply in circuit communication with said CPU and said power management processor comprising circuitry for selectively providing system power from an external source to said computer system responsive to said power management processor, characterized by having a first power supply state and a second power supply state, and further characterized by having circuitry for providing auxiliary power to said power management processor;
• (d) a non-volatile storage device in circuit communication with said CPU for storing data;
• wherein said first power supply state is characterized by said power supply providing system power to said computer system and auxiliary power to said power management processor from said external source;
• and
• wherein said second power supply state is characterized by said power supply not providing system power to said computer system from said external source and said power supply providing auxiliary power to said power management processor from said external source;
• (1) wherein said power management processor is further characterized by causing said power supply to transition from said first power supply state to said second power supply state responsive to at least one of a predetermined set of conditions;
• (2) wherein said power management processor is further characterized by interrupting said CPU by activating said CPU's system management interrupt prior to causing said power supply to transition from said first power supply state to said second power supply state;
• and
• (3) wherein said CPU is further configured to perform at least one predetermined set of tasks responsive to said power management processor interrupting said CPU via said system management interrupt and prior to said power supply transitioning from said first power supply state to said second power supply state, said at least one predetermined set of tasks including said CPU storing data to said non-volatile storage device.