Power management system distinguishing between primary and secondary system activity

A method for managing power within a computer system including a processor rated for a maximum clock frequency, a peripheral device, and a clock generator for providing a CPU clock signal to said processor and a system clock signal to said peripheral device, said method comprising the steps of:

• initially driving said CPU clock signal at said maximum clock frequency;
• monitoring said computer system for an occurrence of either a primary activity or a secondary activity;
• driving said CPU clock signal at said maximum clock frequency if said primary activity is detected;
• driving said CPU clock signal at a reduced frequency if said primary activity does not occur within a first predetermined time period;
• driving said CPU clock signal at said maximum clock frequency for a second predetermined time period if said secondary activity occurs while said CPU clock signal is driven at said reduced frequency, and again driving said CPU clock signal at said reduced frequency following said second predetermined time period;
• and
• stopping said CPU clock signal if said primary activity does not occur within a third predetermined time period following initiation of said step of driving said CPU clock signal at a reduced frequency.

A power management unit for a computer system, wherein said computer system includes a processor rated for a maximum clock frequency, at least one peripheral device, and a clock generator for providing a CPU clock signal to said processor and a system clock signal to said peripheral device, wherein said power management unit comprises:

• a clock control unit configured to selectively vary the frequency of said CPU clock signal and said system clock signal;
• a system monitor configured to detect a primary activity of said computer system and a secondary activity of said computer system;
• and
• a power management state machine coupled to said clock control unit and to said system monitor, wherein said power management state machine includes a first state during which said clock control unit is invoked to drive said CPU clock signal at said maximum clock frequency, a second state during which said clock control unit is invoked to drive said CPU clock signal at a slower frequency, a third state during which said clock control unit is invoked to stop said CPU clock signal, and a transitory state during which said clock control unit is invoked to drive said CPU clock signal at said maximum clock frequency for a predetermined time;
• wherein an occurrence of said primary activity causes said power management state machine to enter said first state;
• and
• time-out counter circuitry coupled to said system monitor and to said power management state machine, wherein when said power management state machine is in said first state, said time-out counter circuitry is configured to determine whether a first subsequent primary activity, subsequent to said first primary activity, has been detected by said system monitor within a first predetermined lapse of time;
• wherein said power management state machine transitions from said first state to said second state if said first subsequent primary activity does not occur within said first predetermined lapse of time;
• wherein when said power management state machine is in said second state, said time-out counter circuitry is configured to determine whether a second subsequent primary activity, subsequent to said first subsequent primary activity, has been detected by said system monitor within a first predetermined lapse of time;
• wherein said power management state machine transitions from said second state to said third state if said first subsequent primary activity does not occur within said first predetermined lapse of time;
• wherein said power management state machine transitions from said second state to said transitory state if said secondary activity is detected while said power management state machine is in said second state, and wherein said power management state machine reverts back to said second state following said predetermined time;
• and
• wherein said power management state machine transitions from said third state to said transitory state if said secondary activity is detected while said power management state machine is in said third state, and wherein said power management state machine reverts back to said third state following said predetermined time.