US 5,511,202 A · Desktop computer system having zero-volt system suspend and control unit for ascertaining interrupt controller base address · patentgrep

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Abstract

A desktop computer system having the capability to suspend and resume the state of the computer system. The suspended system state is saved to the system hard file such that system power may be removed, effectively allowing a system suspend requiring no power from the power supply.

Drawings

Claims5

Dependent claims

A desktop computer system for running an operating system and an application program, the system having a BIOS and comprising:

(a) a CPU;
(b) volatile system memory in circuit communication with said CPU and for storing memory data;
(c) an interrupt controller in circuit communication with said CPU, said interrupt controller being capable of processing a plurality of interrupt events in coordination with said CPU, said interrupt controller having a first set of interrupt vectors associated therewith and located in said volatile system memory, said interrupt controller having a first set of interrupt service routines associated therewith and located in said volatile system memory, and said interrupt controller having at least one internally-located write-only register for storing at least one base address corresponding to the first set of interrupt vectors and the first set of interrupt service routines;
and
(d) a control unit in circuit communication with said CPU and for determining the state of said at least one internally-located write-only register responsive to a preselected suspend event;
said control unit determining the state of the at least one base address of said interrupt controller by:
(i) writing a second set of interrupt vectors to said volatile system memory;
(ii) writing a second set of interrupt service routines to said volatile system memory, each of the second set of interrupt service routines corresponding to at least one of the interrupt vectors from the second set of interrupt vectors;
then
(iii) generating an interrupt event to be serviced by one of the second set of interrupt service routines corresponding to at least one of the interrupt vectors from the second set of interrupt vectors;
(iv) processing the interrupt event in coordination with said interrupt controller;
then
(v) servicing the interrupt with one of the interrupt service routines corresponding to at least one of the interrupt vectors from the second set of interrupt vectors;
and then
(vi) determining the state of the at least one base address of said interrupt controller from the state of said volatile system memory after said step of servicing the interrupt.

12 more elements

A desktop computer system for running an operating system and an application program, the system having a BIOS and comprising:

(a) a CPU;
(b) a power supply having circuitry for selectively providing system power from an external source to said computer system, said power supply having a first power supply state and a second power supply state;
(c) a non-volatile storage device in circuit communication with said CPU;
(d) volatile system memory in circuit communication with said CPU and for storing memory data;
(e) an interrupt controller in circuit communication with said CPU, said interrupt controller being capable of processing a plurality of interrupt events in coordination with said CPU, said interrupt controller having a first set of interrupt vectors associated therewith and located in said volatile system memory, said interrupt controller having a first set of interrupt service routines associated therewith and located in said volatile system memory, and said interrupt controller having at least one internally-located write-only register for storing at least one base address corresponding to the first set of interrupt vectors and the first set of interrupt service routines;
(f) volatile system registers in circuit communication with said CPU and for storing register data;
and
(g) a control unit in circuit communication with said CPU and for selectively changing the state of said computer system between a normal operating state and a suspend state responsive to a preselected suspend event;
(1) said normal operating state being characterized by said power supply being in said first power supply state and said computer system being capable of executing said application program responsive to user commands or to the operating system or the BIOS;
(2) said suspend state being characterized by the register data and the memory data being stored on said non-volatile storage device and said power supply being in said second power supply state;
(3) said change between said normal operating state and said suspend state including said control unit copying the memory data and the register data from said system memory and said system registers to said non-volatile storage device responsive to said preselected suspend event;
(4) said power supply changing between said power supply states responsive to said control unit;
(5) said change between said normal operating state and said suspend state further including said control unit causing said power supply to change between said first power supply state and said second power supply state, respectively, responsive to said preselected suspend event;
and
(6) said control unit ascertaining the state of the at least:
one base address of said interrupt controller by:
(i) writing a second set of interrupt vectors to said volatile system memory;
(ii) writing a second set of interrupt service routines to said volatile system memory, each of the second set of interrupt service routines corresponding to at least one of the interrupt vectors from the second set of interrupt vectors;
then
(iii) generating an interrupt event to be serviced by one of the second set of interrupt service routines corresponding to at least one of the interrupt vectors from the second set of interrupt vectors;
(iv) processing the interrupt event in coordination with said interrupt controller;
then
(v) servicing the interrupt with one of the interrupt service routines corresponding to at least one of the interrupt vectors from the second set of interrupt vectors;
and then
(vi) determining the state of the at least one the base address of said interrupt controller from the state of said volatile system memory after said step of servicing the interrupt.

22 more elements

A desktop computer system for running an operating system and an application program, the system having a BIOS and comprising:

(a) a CPU;
(b) a power supply having circuitry for selectively providing system power from an external source to said computer system, said power supply having a first power supply state and a second power supply state;
(c) a non-volatile storage device in circuit communication with said CPU;
(d) volatile system memory in circuit communication with said CPU and for storing memory data;
(e) an interrupt controller in circuit communication with said CPU, said interrupt controller being capable of processing a plurality of interrupt events in coordination with said CPU, said interrupt controller having a first set of interrupt vectors associated therewith and located in said volatile system memory, said interrupt controller having a first set of interrupt service routines associated therewith and located in said volatile system memory, and said interrupt controller having at least one internally-located write-only register for storing at least one base address corresponding to the first set of interrupt vectors and the first set of interrupt service routines;
(f) volatile system registers in circuit communication with said CPU and for storing register data;
and
(g) a control unit in circuit communication with said CPU and for selectively changing the state of said computer system between a normal operating state and a suspend state responsive to a preselected suspend event;
(1) said normal operating state being characterized by said power supply being in said first power supply state and said computer system being capable of executing said application program responsive to user commands or to the operating system or the BIOS;
(2) said suspend state being characterized by the register data and the memory data being stored on said non-volatile storage device and said power supply being in said second power supply state;
(3) said change between said normal operating state and said suspend state including said control unit copying the memory data and the register data from said system memory and said system registers to said non-volatile storage device responsive to said preselected suspend event;
(4) said power supply changing between said power supply states responsive to said control unit;
(5) said change between said normal operating state and said suspend state further including said control unit causing said power supply to change between said first power supply state and said second power supply state, respectively, responsive to said preselected suspend event;
(6) said power supply further having circuitry for providing auxiliary power to said computer system;
(7) said first power supply state being characterized by said power supply providing system power and auxiliary power to said computer system from said external source;
(8) said second power supply state being characterized by said power supply not providing system power to said computer system from said external source and said power supply providing auxiliary power to said computer system from said external source;
and
(9) said control unit ascertaining the state of the at least one base address of said interrupt controller by:
(i) writing a second set of interrupt vectors to said volatile system memory;
(ii) writing a second set of interrupt service routines to said volatile system memory, each of the second set of interrupt service routines corresponding to at least one of the interrupt vectors from the second set of interrupt vectors;
then
(iii) generating an interrupt event to be serviced by one of the second set of interrupt service routines corresponding to at least one of the interrupt vectors from the second set of interrupt vectors;
(iv) processing the interrupt event in coordination with said interrupt controller;
then
(v) servicing the interrupt with one of the interrupt service routines corresponding to at least one of the interrupt vectors from the second set of interrupt vectors;
and then
(vi) determining the state of the at least one base address of said interrupt controller from the state of said volatile system memory after said step of servicing the interrupt.

24 more elements

A desktop computer system for running an operating system and an application program, the system having a BIOS and comprising:

(a) a CPU;
(b) a power supply having circuitry for selectively providing system power from an external source to said computer system, said power supply having a first power supply state and a second power supply state;
(c) a non-volatile storage device in circuit communication with said CPU;
(d) volatile system memory in circuit communication with said CPU and for storing memory data;
(e) an interrupt controller in circuit communication with said CPU, said interrupt controller being capable of processing a plurality of interrupt events in coordination with said CPU, said interrupt controller having a first set of interrupt vectors associated therewith and located in said volatile system memory, said interrupt controller having a first set of interrupt service routines associated therewith and located in said volatile system memory, and said interrupt controller having at least one internally-located write-only register for storing at least one base address corresponding to the first set of interrupt vectors and the first set of interrupt service routines;
(f) volatile system registers in circuit communication with said CPU and for storing register data;
(g) a control unit in circuit communication with said CPU for selectively changing the state of said computer system between a normal operating state and a suspend state responsive to a preselected suspend event, and for selectively changing the state of said computer system between the suspend state and the normal operating state responsive to at least one predetermined resume event;
and
(h) a boot unit in circuit communication with said CPU and said control unit, said boot unit capable of execution by said CPU to perform at least a first predetermined boot task responsive to said at least one predetermined resume event;
(1) said normal operating state being characterized by said power supply being in said first power supply state and said computer system being capable of executing said application program responsive to user commands or to the operating system or the BIOS;
(2) said suspend state being characterized by the register data and the memory data being stored on said non-volatile storage device and said power supply being in said second power supply state;
(3) said change between said normal operating state and said suspend state including said control unit copying the memory data and the register data from said system memory and said system registers to said non-volatile storage device responsive to said preselected suspend event;
(4) said power supply changing between said power supply states responsive to said control unit;
(5) said change between said normal operating state and said suspend state further including said control unit causing said power supply to change between said first power supply state and said second power supply state, respectively, responsive to said preselected suspend event;
(6) said control unit ascertaining the state of the at least one base address of said interrupt controller by:
(i) writing a second set of interrupt vectors to said volatile system memory;
(ii) writing a second set of interrupt service routines to said volatile system memory, each of the second set of interrupt service routines corresponding to at least one of the interrupt vectors from the second set of interrupt vectors;
then
(iii) generating an interrupt event to be serviced by one of the second set of interrupt service routines corresponding to at least one of the interrupt vectors from the second set of interrupt vectors;
(iv) processing the interrupt event in coordination with said interrupt controller;
then
(v) servicing the interrupt with one of the interrupt service routines corresponding to at least one of the interrupt vectors from the second set of interrupt vectors;
and then
(vi) determining the state of the at least one base address of said interrupt controller from the state of said volatile system memory after said step of servicing the interrupt.

21 more elements

A desktop computer system for running an operating system and an application program, the system having a BIOS and comprising:

(a) a CPU;
(b) a power supply having circuitry for selectively providing system power from an external source to said computer system, said power supply having a first power supply state and a second power supply state;
(c) a non-volatile storage device in circuit communication with said CPU;
(d) volatile system memory in circuit communication with said CPU and for storing memory data;
(e) an interrupt controller in circuit communication with said CPU, said interrupt controller being capable of processing a plurality of interrupt events in coordination with said CPU, said interrupt controller having a first set of interrupt vectors associated therewith and located in said volatile system memory, said interrupt controller having a first set of interrupt service routines associated therewith and located in said volatile system memory, and said interrupt controller having at least one internally-located write-only register for storing at least one base address corresponding to the first set of interrupt vectors and the first set of interrupt service routines;
(f) volatile system registers in circuit communication with said CPU and for storing register data;
(g) a control unit in circuit communication with said CPU for selectively changing the state of said computer system between a normal operating state and a suspend state responsive to a preselected suspend event and for selectively changing the state of said computer system between the suspend state and the normal operating state responsive to at least one predetermined resume event;
and
(h) a boot unit in circuit communication with said CPU and said control unit, said boot unit capable of execution by said CPU to perform at least a first predetermined boot task responsive to said at least one predetermined resume event;
(1) said normal operating state being characterized by said power supply being in said first power supply state and said computer system being capable of executing said application program responsive to user commands or to the operating system or the BIOS;
(2) said suspend state being characterized by the register data and the memory data being stored on said non-volatile storage device and said power supply being in said second power supply state;
(3) said change between said normal operating state and said suspend state including said control unit copying the memory data and the register data from said system memory and said system registers to said non-volatile storage device responsive to said preselected suspend event;
(4) said power supply changing between said power supply states responsive to said control unit;
(5) said change between said normal operating state and said suspend state further including said control unit causing said power supply to change between said first power supply state and said second power supply state, respectively, responsive to said preselected suspend event;
(6) said power supply further having circuitry for providing auxiliary power to said computer system;
(7) said first power supply state being characterized by said power supply providing system power and auxiliary power to said computer system from said external source;
(8) said second power supply state being characterized by said power supply not providing system power to said computer system from said external source and said power supply providing auxiliary power to said computer system from said external source;
and
(9) said control unit ascertaining the state of the at least one base address of said interrupt controller by:
(i) writing a second set of interrupt vectors to said volatile system memory;
(ii) writing a second set of interrupt service routines to said volatile system memory, each of the second set of interrupt service routines corresponding to at least one of the interrupt vectors from the second set of interrupt vectors;
then
(iii) generating an interrupt event to be serviced by one of the second set of interrupt service routines corresponding to at least one of the interrupt vectors from the second set of interrupt vectors;
(iv) processing the interrupt event in coordination with said interrupt controller;
then
(v) servicing the interrupt with one of the interrupt service routines corresponding to at least one of the interrupt vectors from the second set of interrupt vectors;
and then
(vi) determining the state of the at least one base address of said interrupt controller from the state of said volatile system memory after said step of servicing the interrupt.

25 more elements

Dependencies are inferred from the claim text.

Description28,239 words

Summary4,032 words

#The present application is thought to be related to the following pending applications:

#Application Ser. No. 08/097,334, filed Jul. 23, 1993, and entitled "DESKTOP COMPUTER HAVING A SINGLE SWITCH SUSPEND/RESUME FUNCTION" (further identified as Attorney Docket No. BC9-93-018 (21322/00158));

#Application Ser. No. 08/097,246, filed Jul. 23, 1993, and entitled "METHOD OF SAVING AND RESTORING THE STATE OF A CPU EXECUTING CODE IN A PROTECTED MODE" (further identified as Attorney Docket No. BC9-93-017 (21322/00162)); and

Brief description of the drawings15 figures

#In the accompanying drawings, which are incorporated in and constitute a part of this specification, embodiments of the invention are illustrated, which, together with a general description of the invention given above, and the detailed description given below serve to example the principles of this invention.

#FIG. 1 is a perspective view of a personal computer embodying this invention;

#FIG. 2 is an exploded perspective view of certain elements of the personal computer of FIG. 1 including a chassis, a cover, an electromechanical direct access storage device and a planar board and illustrating certain relationships among those elements;

Detailed description23,853 words

#While the present invention will be described more fully hereinafter with reference to the accompanying drawings, in which a preferred embodiment of the present invention is shown, it is to be understood at the outset of the description which follows that persons of skill in the appropriate arts may modify the invention here described while still achieving the favorable results of this invention. Accordingly, the description which follows is to be understood as being a broad, teaching disclosure directed to persons of skill in the appropriate arts, and not as limiting upon the present invention. The present invention deals with the complete design of a computer system, including, but not limited to computer architecture design, digital design, BIOS design, protected mode 80486 code design, application code design, operating system code design, and Advanced Power Management advanced programming interface usage. This application is written for those very familiar with all aspects of computer system design.

#Referring now more particularly to the accompanying drawings, a microcomputer system embodying the present invention is there shown and generally indicated at 10 (FIG. 1). As mentioned hereinabove, the computer 10 may have an associated monitor 11, keyboard 12, mouse 13, and printer or plotter 14. The computer 10 has a cover 15 formed by a decorative outer member 16 (FIG. 2) and an inner shield member 18 which cooperate with a chassis 19 in defining an enclosed, shielded volume for receiving electrically powered data processing and storage components for processing and storing digital data. At least certain of these components are mounted on a multilayer planar 20 or motherboard which is mounted on the chassis 19 and provides a means for electrically interconnecting the components of the computer 10 including those identified above and such other associated elements as floppy disk drives, various forms of direct access storage devices, accessory cards or boards, and the like. As pointed out more fully hereinafter, provisions are made in the planar 20 for the passage of input/output signals to and from the operating components of the microcomputer.

#The computer system has a power supply 17 and a power button 21, also hereinafter the switch 21. Unlike in the usual power switch in a typical system, the power button 21 does not switch unregulated line power to and from the power supply 17, as will be explained below. The chassis 19 has a base indicated at 22, a front panel indicated at 24, and a rear panel indicated at 25 (FIG. 2). The front panel 24 defines at least one open bay (and in the form illustrated, four bays) for receiving a data storage device such as a disk drive for magnetic or optical disks, a tape backup drive, or the like. In the illustrated form, a pair of upper bays 26, 28 and a pair of lower bays 29, 30 are provided. One of the upper bays 26 is adapted to receive peripheral drives of a first size (such as those known as 3.5 inch drives) while the other 28 is adapted to receive drives of a selected one of two sizes (such as 3.5 and 5.25 inch) and the lower bays are adapted to receive devices of only one size (3.5 inch). One floppy disk drive is indicated at 27 in FIG. 1, and is a removable medium direct access storage device capable of receiving a diskette inserted thereinto and using the diskette to receive, store and deliver data as is generally known. One hard disk drive is indicated at 31 and is a fixed medium direct access storage device capable of storing and delivering data as is generally known.