Method and apparatus for providing an enhanced programmable priority interrupt controller

An improved advanced programmable interrupt controller (APIC controller) comprising:

• a plurality of means for storing eight bit programmable interrupt vectors indicating an address of an interrupt in memory and its priority,
• means, coupled to said storing meads, for transferring a message containing one of said interrupt vectors,
• logic means, coupled to said transferring means, for determining if said message being transferred is directed to an APIC controller and
• means, coupled to said logic means, for executing interrupt vectors in an order based on a priority level which is encoded in five least significant bits of said interrupt vector.

A computer system comprising:

• a central processing unit;
• main memory;
• a bus for transferring data, addresses, and control signals;
• and
• an improved advanced programmable interrupt controller (APIC controller) connected to receive signals on the bus and to transfer interrupt signals to the central processing unit comprising:
• an input/output unit including a redirection table with a plurality of registers for storing eight bit programmable interrupt vectors indicating an address of an interrupt in memory and its priority,
• circuitry for transferring a message containing an interrupt vector,
• logic circuitry for determining if a message being transferred containing an interrupt vector is directed to said APIC controller, and
• circuitry for executing interrupt vectors in an order based on a priority level which is encoded in five least significant bits of the interrupt vectors.

A computer system comprising:

• a central processing unit;
• main memory;
• a bus, coupled to the central processing unit and to the main memory, for transferring data, addresses, and control signals;
• and
• an improved advanced programmable interrupt controller (APIC controller) coupled to receive signals on the bus and to transfer interrupt signals to the central processing unit comprising:
• a plurality of means for storing eight bit programmable interrupt vector indicating an address of an interrupt in memory and its priority,
• means for transferring a message containing an interrupt vector,
• logic means for determining if a message being transferred containing an interrupt vector is directed to an APIC controller, and
• means, coupled to the central processing unit and to the logic means, for executing interrupt vectors in an order based on a priority level which is encoded in five least significant bits of the interrupt vector.

A method for processing interrupts in a computer system including a central processing unit;

• main memory;
• a bus for transferring data, addresses, and control signals;
• and an improved advanced programmable interrupt controller (APIC controller) connected to receive signals on the bus and to transfer interrupt signals to the central processing unit comprising the steps of:
• receiving an interrupt signal at a redirection table of the APIC controller,
• generating an interrupt vector for the interrupt signal with the five least significant bits designating the priority of the interrupt signal,
• sending the interrupt vector to the APIC controller,
• comparing the priority within the received interrupt vector with the priority of any interrupt vector being executed under control of the APIC controller by comparing the five least significant bits of each interrupt vector, and
• executing the received interrupt vector in accordance with the comparison.