Method for controlling the operation of a computer implemented apparatus to selectively execute instructions of different bit lengths

A method for selectively controlling the operation of a computer-implemented apparatus including means within said computer-implemented apparatus such that a software program when executed by a computer enables said computer to selectively execute instructions of a first predetermined bit length and instructions of a second predetermined bit length comprising the steps of:

• storing a plurality of said instructions of at least one of said first predetermined bit length and said second predetermined bit length in contiguous locations within a memory;
• providing first register means containing an even instruction execution pointer having a value pointing at a first one of said plurality of said instructions;
• providing second register means containing an odd instruction execution pointer at one of said plurality of said instructions that is adjacent to said first one of said plurality of said instructions;
• said computer executing said first one of said plurality of said instructions and changing the value of said even instruction execution pointer by some amount in order to point said even instruction execution pointer to another one of said plurality of said instructions and executing said one instruction adjacent to said first one of said plurality of said instructions and changing the value of said odd instruction execution pointer by said amount in order to point said odd instruction execution pointer to yet another one of said plurality of said instructions, said changing the value of said even instruction execution pointer alternating with said changing the value of said odd instruction execution pointer in order to cause said computer to execute each of said plurality of said instructions in at least one of a first and a second manner;
• said first manner of executing occurring when one of said even and said odd instruction execution pointers point to an instruction having a portion therein that signals said first manner of execution to said computer, said first manner of execution causing said computer to execute said instruction by itself, said instruction having said first predetermined bit length;
• and
• said second manner of execution occurring when one of said even and said odd instruction execution pointers point to an instruction having a portion therein that signals said second manner of execution to said computer, said second manner of execution causing said computer to simultaneously execute the instruction to which said even instruction execution pointer is pointing and the instruction to which said odd instruction execution pointer is pointing, said simultaneous execution of instructions corresponding to said execution of said instruction of said second predetermined bit length.